This is new and at the concept stage. If you have ideas, PLEASE drop me an e-mail at:
jcooley@TheWorld.com or call (508) 429-4357 to talk directly with me. - John
|
- 0-in status & Kurt Baty
-
Gadfly 03/00,
ESNUG 346 #15,
348 #18
|
- Aart & Harvey, the goats
-
ESNUG 194 #0,
199 #0,
207 #0, "Ewald" born
ESNUG 217 #0,
231 #0, trouble!
ESNUG 234 #0
|
- adders, engineers discuss 7 types of
-
ESNUG 343 #13
|
- Ambit RTL synthesis vs. Synopsys DC, early year 2000 customer stats for
-
SNUG'00 #9
|
- Analysts (Wall St.), PKS, Magma, & PhysOpt
-
147 Wall St. types monitor ESNUG
ESNUG 391 #9, what about
PhysOpt?
339 #2,
340 #1, what about
PhysOpt with or without PKS?
360 #1, what about
Numerical Tech RET?
372 #1,
380 #3,
Magma, Merrill Lynch, Goldman Sachs
DAC'01 #28,
Wall St. monitoring Chip Architect and Hidden Dragon
SNUG'02 #16
thoughts on SNPS shares
ESNUG 400 #14,
Wall St., Calibre, Hercules, and Cadence DRC/LVS
DAC 01 #33
|
- Avanti Apollo vs. Cadence Silicon Ensemble, use stats for
-
SNUG'00 #12
|
- AWK - SED - grep, running UNIX utilities on Windows like
-
ESNUG 309 #6
|
- asynchronous RAMs, creating a single cycle Write for
-
ESNUG 261 #7,
ESNUG 274 #5
|
- C/C++ Based Hardware Design, the folly of
-
DAC'99 #5,
DAC'99 #6,
DAC'99 #7, CynApps
ESNUG 326 #2,
328 #2, SystemC
ESNUG 334 #8,
335 #9,
338 #9,
344 #8,
345 #10,
346 #8,
353 #3,
|
- Certify to FPGA prototype, customers like Synplicity
-
ESNUG 343 #6
|
- Chip Architect, the rise and fall of
-
ESNUG 338 #1,
Wall St. monitoring Chip Architect and Hidden Dragon
SNUG'02 #16
|
- Chip Express, we got burned by
-
ESNUG 299 #2,
300 #1, co. responds
ESNUG 301 #1,
305 #8, gory details
ESNUG 306 #2
|
- clock doubler circuit, a simple digital
-
ESNUG 308 #12
|
- clock-less design, the strange art of
-
EDSGN 05/09/00
|
- ClockWise, initial customer thoughts on Ultima's
-
ESNUG 350 #3,
Gadfly 05/00,
ESNUG 352 #1,
353 #2
|
- custom PrimeTime timing reports with TCL
-
ESNUG 331 #3
|
- CynApps CynLib vs. Synopsys SystemC
-
SNUG'00 #13,
ESNUG 351 #4,
DAC'99 #5,
ESNUG 326 #2, init user impressions of CynLib
328 #2,
344 #8
|
- DAC Trip Reports
-
DAC'99,
DAC'98,
DAC'96,
DAC'95,
DAC'94
|
- DesignSync, nightmares with Synchronicity's
-
ESNUG 345 #5,
ESNUG 345 #4
|
- DC 99.10 "set_dont_touch_network" bug
-
ESNUG 342 #2,
343 #1,
344 #7,
353 #1
|
- DC 99.05 & DC 99.10, three bugs that cause bad logic to be synthesized in
-
ESNUG 348 #1,
349 #4,
349 #1
|
- DRAM memory testing algorithms
-
ESNUG 309 #4
|
- ECO Compiler, the rise & fall of
-
ESNUG 267 #3,
268 #1,
280 #1, Avanti Saturn and
ESNUG 292 #1,
295 #3,
SNUG'99 #30, ECO Compiler unworkable
SNUG'99 #36, probable end of
SNUG'00 #21
|
- EMACS mode for dc_shell
-
ESNUG 351 #6
|
- "fake" subdesigns, the advantages of crafting DC libs that have
-
ESNUG 340 #3,
341 #5
|
- fault coverage, transmission gates ruin
-
ESNUG 316 #3,
320 #10
|
- fault-tolerant design, books/URLs/ideas for
-
ESNUG 353 #8
|
- FlexRoute, first customer review of
-
ESNUG 331 #1,
336 #1,
337 #1
|
- Formality vs. Verplex vs. Chrysalis vs. FormalPro
- early Verplex kicking Formality and Avanti Chrysalis butt
ESNUG 322 #8,
SNUG'99 #31,
331 #6,
333 #1,
334 #1,
335 #10,
SNUG'00 #21,
Verplex still ahead at DAC'01
DAC'01 #16,
ESNUG 380 #4,
Synopsys Formality starts making a comeback
ESNUG 381 #11,
383 #15,
389 #8,
371 #11,
372 #8,
394 #4,
401 #6,
SNUG'02 #10,
Mentor's FormalPro suddenly joins the game
ESNUG 373 #9,
394 #7,
403 #6,
Synopsys kills off Chrysalis
404 #8
|
- FPGAs, self-programming or "breeding"
-
ESNUG 276 #0,
277 #1
|
- free/shareware EDA tools, sources for
-
EDSGN
|
- full_case/parallel_case, the evil twins of synthesis
-
ESNUG 332 #1,
334 #2,
337 #3,
338 #8,
339 #3
|
- Gerry Hsu, Stalin of the EDA world
-
(censored) Industry Gadfly,
ESNUG 351 #9, 1996
Gadfly
|
- hardware emulators, last known (1996) user comparisions of
Quickturn, Aptix, Meta-Systems, (defunct) Arkos
-
ESNUG 246 #8,
247 #3,
248 #8,
249 #1,
255 #2,
262 #6,
262 #7,
262 #11, if you
have more current data, e-mail me!!!
|
- the hierarchical vs. flat layout religious war
-
ESNUG 336 #1,
337 #1,
338 #4,
340 #7,
SNUG'00 #5
|
- Library Compiler, putting text strings inside db's for
-
ESNUG 307 #11,
308 #2
|
- license-fetching, Synopsys TCL script for
-
ESNUG 339 #9
|
- LogicVision's memBIST-IC vs. Mentor's MBistArchitect
-
ESNUG 348 #4,
351 #2,
SNUG'00 #20,
ESNUG 289 #13,
291 #4,
290 #4,
292 #5,
303 #11,
304 #13,
309 #3,
310 #5
|
- LSF, creating SUN compute farms with
-
ESNUG 308 #7,
310 #11,
ESNUG 311 #2, white paper
312 #1,
315 #5, ACS
ESNUG 336 #2, SUN
SNUG'00 #22
|
- MacroTest, two customers review Mentor's
-
ESNUG 340 #4
|
- memory BIST tools, designers discussions on
-
ESNUG 348 #4,
351 #2,
SNUG'00 #20,
ESNUG 289 #13,
291 #4,
290 #4,
292 #5,
303 #11,
304 #13,
309 #3,
310 #5
|
- "Missing Elf" EDA customer tool usage analysis, (VERA example of)
-
ESNUG 339 #11, see Editor's Note at bottom of
340 #9,
Gadfly 01/00
|
- mixing Windows NT & UNIX, gotchas with
-
ESNUG 289 #2
|
|
- Module Compiler, customers talking about
- first mentions w/ BOA & BRT
ESNUG 273 #3,
274 #2, first customer review
ESNUG 275 #1, angry back & forth
ESNUG 279 #3,
280 #5,
283 #4,
295 #2,
306 #4, intermediate bits
ESNUG 319 #3,
321 #10, tricks w/
ESNUG 322 #5,
325 #8, PhysOpt &
ESNUG 341 #1, encryption &
ESNUG 331 #5, other datapath tools
ESNUG 297 #6,
299 #10,
DAC'99 #44, customer use stats
SNUG'00 #9
|
- multicycle paths, dealing with
-
ESNUG 245 #1,
246 #4,
247 #4,
271 #5, point to point timing exceptions
ESNUG 225 #1,
226 #1, valid paths becoming bogus false paths
ESNUG 316 #1,
318 #7, bi-directional busses & path segmentation
ESNUG 248 #8,
249 #2
|
- nonblocking Verilog assignments; coding styles that kill!
-
ESNUG 347 #1, replies
351 #7
|
- optimal results, making synthesis libs for
-
ESNUG 342 #13,
343 #10,
349 #9
|
- overloading Verilog system tasks (like $finish & $monitor) in VCS
-
ESNUG 344 #13
|
- OVI/VIUF combined, the really stupid new name for
-
OVI/VIUF
|
- phase-locked loops, models & synth of
-
ESNUG 313 #10,
316 #10,
320 #9, synth of
255 #6,
256 #3
|
- Physical Synthesis, customer opposition to
-
ESNUG 346 #1,
348 #3
|
- PhysOpt, multiple customer reviews of
-
DAC'99 #40, nVidia w/ Cadence backend
ESNUG 335 #1,
339 #2,
340 #1,
341 #1, what bugs tell you
Gadfly 02/00,
ESNUG 343 #2, known tape-outs
SNUG'00 #18,
SNUG'00 #4, Matrox w/ Avanti backend
ESNUG 344 #5, SGI w/ IBM backend
ESNUG 345 #1,
345 #4,
346 #5,
EDSGN 05/16/00
|
- pretty printers, Verilog
-
ESNUG 339 #5,
341 #9
|
- pricing models, negative customer reactions to EDA
- (Synopsys 8/99 price increase)
ESNUG 326 #1,
327 #2, like Ambit-RTL price cut
ESNUG 329 #1,
330 #1,
331 #2, Ambit-RTL too pricey
ESNUG 333 #2, Cadence FAM model
Gadfly 12/99
|
- PrimeTime, 21 gotchas with
-
ESNUG 315 #8
|
- propagate_constraints, the joys & headaches of
-
ESNUG 317 #6,
322 #13
|
- Renoir vs. Escalade vs. Summit, user grumblings on graphical design entry tools
-
Gadfly 1996,
ESNUG 278 #3,
281 #3,
283 #9,
285 #5,
288 #10,
289 #4,
291 #12,
300 #9,
306 #10,
307 #7,
310 #12,
311 #3,
314 #9, market shakeout
DAC'99 #18,
ESNUG 323 #1,
327 #11,
328 #5, newbie Escalade issues
ESNUG 353 #7
|
- (Keating's) "Reuse Methodology Manual" book, customers review/discuss
-
ESNUG 297 #12,
298 #1,
299 #6,
300 #8
|
- revision control software - Clearcase, RCS, SCCS, Cliosoft, & CVS
-
ESNUG 279 #1,
281 #7,
342 #3,
345 #5
|
- Sapphire's FormIT, first customer impressions of
-
EDSGN 05/12/00
|
- Silicon Ensemble, 0.18 um cross-cap problems in Cadence's
-
ESNUG 348 #6,
349 #11,
349 #3
|
- Silicon Perspective, first impressions of
-
EDSGN 05/12/00
|
- Simplex 'Thunder & Lightning', 11 flaws with
-
ESNUG 324 #2,
329 #2, Simplex response
333 #3,
DAC'99 #8
|
- Smith's famous ASIC book on-line
-
DAcafe
|
- SNUG Trip Reports
-
SNUG'00,
SNUG'99,
SNUG'98 (I),
SNUG'98 (II),
SNUG'97
|
- Solidify, customer scuttlebutt on HDAC's
-
dac99 #47
|
- SST Velocity, Siemens use of Mentor's
-
EDSGN 05/15/00
|
- "symbolic simulation", Innologic Systems' strange
-
SNUG'00 #8
|
- Synchronicity's DesignSync, nightmares with
-
ESNUG 345 #5,
ESNUG 345 #4
|
- TCL, horror stories & mistakes to avoid while learning or using
-
ESNUG 317 #7,
321 #1,
334 #9,
335 #7,
343 #12,
348 #17, Design Analyzer chokes
ESNUG 344 #9,
345 #11, Tcl vim
ESNUG 329 #12, FPGA Express TCL bug
ESNUG 345 #8, PrimeTime "transcript" TCL translator
ESNUG 327 #13,
328 #3,
311 #9
|
- TCL, making custom PrimeTime timing reports with
-
ESNUG 331 #3
|
- TetraMax over FastScan, customers gush about
- first mention
DAC'99 #41,
DAC'99 #43,
ESNUG 342 #9, switched from FastScan
343 #7, user class attendance
SNUG'00 #3, market share
SNUG'00 #20
|
- tri-state logic, the endless debate on
-
Gadfly
|
- "Verification Guild" newletter, the latest
-
VG's latest
|
- Verilint (Nova-Explore-RTL), customer disgust at
- great beginnings
ESNUG 230 #6,
232 #2,
239 #1, Avanti makes it ugly
ESNUG 319 #9,
Avanti renames Verilint to Nova-RTL
DAC'99 #19,
DAC'99 #20,
ESNUG 319 #9,
321 #3,
322 #1, Veritools' HDLlint
ESNUG 329 #10,
339 #8, Verisity's SureLint
ESNUG 345 #2,
348 #16
|
- Verilog vs. VHDL, U.S. year 2000 user stats for
-
SNUG'00 #7
|
- Verisity Specman vs. Synopsys VERA
- VERA fiasco
EET 01/03/00,
ESNUG 339 #10,
339 #11,
340 #09
|
- Verisity (Specman) User's Group meeting,
customer review of the year 2000
-
ESNUG 350 #11
|
- Verplex vs. Formality vs. Chrysalis vs. FormalPro
- early Verplex kicking Formality and Avanti Chrysalis butt
ESNUG 322 #8,
SNUG'99 #31,
331 #6,
333 #1,
334 #1,
335 #10,
SNUG'00 #21,
Verplex still ahead at DAC'01
DAC'01 #16,
ESNUG 380 #4,
Synopsys Formality starts making a comeback
ESNUG 381 #11,
383 #15,
389 #8,
371 #11,
372 #8,
394 #4,
401 #6,
SNUG'02 #10,
Mentor's FormalPro suddenly joins the game
ESNUG 373 #9,
394 #7,
403 #6,
Synopsys kills off Chrysalis
404 #8
|
- Wall St. Analysts, PKS, Magma, & PhysOpt
-
147 Wall St. types monitor ESNUG
ESNUG 391 #9, what about
PhysOpt?
339 #2,
340 #1, what about
PhysOpt with or without PKS?
360 #1, what about
Numerical Tech RET?
372 #1,
380 #3,
Magma, Merrill Lynch, Goldman Sachs
DAC'01 #28,
Wall St. monitoring Chip Architect and Hidden Dragon
SNUG'02 #16
thoughts on SNPS shares
ESNUG 400 #14,
Wall St., Calibre, Hercules, and Cadence DRC/LVS
DAC 01 #33
|
- X's, resets, and Verilog 'case' statements
-
ESNUG 338 #8,
339 #3
|
|
