PhysOpt-Avanti Interface

This webpage is for those within the company using Apollo with PhysOpt.

PhysOpt is a synthesis, optimization and placement tool. It takes an RTL or gate level design, with logical/physical libraries and an initial floorplan (in PDEF), and creates an optimized netlist with complete placement that can be routed by using any detail router. This interface is composed of three Scheme scripts that are run within the Avanti environment. The scripts are called readPDEF3.scm, dumpPDEF3.scm, and dumpPLIB.scm.

PhysOpt - Avanti flow diagram

The following figure shows a general flow that uses DC (if used), PhysOpt, and Avanti. PhysOpt shares the same database and environment with DC but it also needs plib/pdb and the floorplan in IEEE PDEF as the inputs.



As you can see in the diagram, the physical library must first be extracted from the Avanti Milkyway database and translated to the Synopsys plib format.  Next, any floorplan information must be translated into PDEF.  Finally, after PhysOpt does its thing, the placed netlist must be fed back into Apollo and it does its magic.

Physical library translation:

PLIB is the Synopsys physical library format. Most ASIC and library vendors, however, only provide libraries in LEF or Milkyway formats to their customers. PhysOpt provides a LEF  translator. For Milkyway databases, use the script "dumpPLIB.scm". This script is run in the Apollo environment and translates Milkyway library data to the plib format directly. This will look something like this:
load dumpPLIB.scm define plibSiteName "tsm3site" dumpPLIB /home/tsmc18/avanti/tsmc18 tsmc18.plib
In this example, the physical library you want to translate is called "tsmc18". The site name is called "tsm3site", the output plib file name is called "tsmc18.plib" The output plib, by default, contains both the technology section and the cell section.

Controlling cell and technology data output:

If you want to dump only the technology section, (or only the cell section,) there is a variable  to control that.

Controlling bus naming style:

In some cases, users want to have control over the bus naming style used in the physical library for PhysOpt, which could be different than what is used in Avanti physical library. There is a variable to control the bus naming style and there are four options:

          plibDumpBusNameRule "[%d]" | "(%d)" | "{%d}" | "<%d>"

Example:
define plibDumpBusNameRule "[%d]" dumpPLIB /home/tsmc18/avanti/tsmc18 tsmc18.plib

Known issues:

Floorplan translation:

For the design floorplan format PhysOpt uses IEEE PDEF. Although Avanti supports PDEF 2.0 or 3.0, the PDEF file written out from Apollo does not contain all the information needed to run Physical Compiler. Hence, it is still recommended to use the Apollo script "dumpPDEF3.scm" to translate the floorplan created in Apollo or Planet. To output the PDEF for the floorplan The following information in the floorplan will be translated into IEEE PDEF.

Known issues:

  • The design cell used to translate the floorplan and placement should not contain detailed routing. Otherwise it would take very long time to run this script. Power or clock pre-routes are okay.
  • Currently this script cannot translate routing blockage that are created by using Apollo's Route Guide due to limitation of the Milkyway database access. You can  use the TCL command 'create_obstruction' in psyn_shell to create routing blockages.
  • This script dumps complete cell instance and net names from the Milkyway database. Sometimes the names may not correspond to what are used in PhysOpt and it creates errors when reading in the PDEF in psyn_shell. For example, you might experience problems with escape sign (\) that is added in front of hierarchy separators and/or bus names. A simple perl script should be able to resolve this kind of problems.

    • Translation of PhysOpt's placement to Avanti

    After PhysOpt run is complete, it writes out an updated IEEE PDEF file which contains complete placement and the original floorplan. Then, you can use the Apollo script "readPDEF3.scm" to translate PhysOpt's placement back to Apollo.  
    This script  converts and load PhysOpt's placement. In addition, you need to take the output gate-level netlist from PhysOpt to Apollo, create a new design library and a new design cell. The new cell created does not have to have the original floorplan loaded because the output PDEF from PhysOpt contains the original floorplan. "readPDEF3.scm" will recover the original floorplan and then load the placement into the specified design cell.

    To read the PDEF for the design back into Apollo:

    After this script is done, it updates and automatically saves the new design cell. You can then open this design cell in Apollo and perform global and detailed routing.

    Known issues:

    1. This script does not accept the PDEF which uses NAMEPREFIX for cell instance names. However, the PDEF written out from PhysOpt uses name prefix by default. In order for PhysOpt to write out PDEF with complete instance names instead of using name prefix, you need to set the following variable in psyn_shell. 2. You might experience the same name mapping problem as in the floorplan translation step for the escape sign used in front of the hierarchy separators and/or bus names. Apollo may report unfounded cell instances in this case. Again, you should be able to resolve this by using a simple perl script.   3. Although some users prefer to use Avanti's ECO capability to update a design library and design cell, it is still recommended to create a new design library and cell for PhysOpt's output.

    Passing timing constraints to Avanti:

    As of release 2000.3 Apollo now supports SDC (1.1) format. You can write out SDC from PhysOpt/DC and load it into the design cell in order to perform CTS or timing-driven routing. There are, however, still many constraints that are not supported by Avanti yet. If you experience problems in loading SDC to Avanti, as an alternative you can use the following DC/PhysOpt commands to write a timing requirement file and load it into the design cell in Apollo.

    Using PhysOpt for post-CTS incremental optimization:

    Designs need to have clock buffer trees. PhysOpt does not have this capability  (although Synopsys claims to be working on it) so clock trees need to be created in the back end by using Apollo's CTS or another tool. Since Apollo automatically performs ECO placement after clock buffers are inserted, it may introduce post-CTS congestion or worsen the timing QoR of the design due to placement disturbance. Therefore, it is sometimes necessary to take the post-CTS design back to PhysOpt to perform legalization of clock buffer placement and/or incremental optimization. To do that you need to perform the following steps.

    Using PhysOpt for post-route incremental optimization:

    After detailed routing, if there is a need, you can also take the design back to PhysOpt to run post-route incremental optimization. To do this you need not only the post-route netlist and the PDEF with complete placement, you also need SDF and set_load/set_resistance files for back annotation. Please note although PhysOpt can perform port route optimization, it does not read in the complete detail routing information.