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A little reminiscing … |
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Introduction to NVIDIA |
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Our Track Record |
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Our Development Philosophy |
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General Methodology Overview |
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Typical Project Timeline |
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Level of Investment |
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When Harry met Sally … |
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What keeps me up at night |
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Where things are going |
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~850 employees – publicly traded NVDA |
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Recognized leader in 3D technology |
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Broad product family |
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20% overall gfx market share and rapidly growing
(48% standalone desktop) |
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Named “100 Most Influential Technology Company”
by Ziff Davis |
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Expanding market - X-Box (consumer), Apple, mobile |
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Design for Correctness, and Time-To-Money |
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Goal of <= 1.5 spins to production |
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< 100 days 1st tapeout to
production |
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Institutionalize best practices and exploit
leverage |
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Constant and ongoing re-evaluation of “what”
& “how” |
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Intellectual honesty, self-criticism |
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Everybody does everything |
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No product has to be perfect. |
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For if not this one then the next … |
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Verilog,
full synthesis, static timing, simulation/emulation/formal |
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1,2,4,8 |
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1 conception, 2 implementations, 4
representations, 8 ways to verify |
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COT flow |
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3rd party std. cells/RAMs, custom
RAMs/PLL/DAC/IO |
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Historical
two designs per technology (~ 1 process/year) |
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Priorities : schedule, performance/area |
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Multiple, overlapped design teams (3 teams, 2 seasons) |
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Constantly evolving methodology, partner with vendors |
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Typical
1.5 year schedule would have: |
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1-2 months specification |
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2-4 months of implementation |
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3-9 months of verification |
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1-2 months of physical design |
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~$85M of CAD tools installed and online |
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over $80M acquired in the last 2-3 years ! |
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$15M - $20M Emulation installation |
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Engineering Compute resources |
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Desktops: 200 Sun/2150 PCs |
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Servers:
278 Sparc/Solaris, 634 x86/Linux, 496 Gbytes Ram |
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14 Tera bytes of storage |
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Digital |
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EMACS and VI !! |
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RTL - Verilog |
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Simulators - Synopsys VCS, Cadence XL & NC,
InnoLogic ESP-XV |
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Emulator - IKOS VLE |
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Synthesis - Synopsys Design Expert, Synopsys
Module Compiler, Synopsys Physical Compiler |
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Test – Synopsys Sunrise, Synopsys TetraMax |
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Timing - Synopsys PrimeTime using SDF/DSPF or
custom wireloads, Mentor Tau |
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Debug – Synopsys Virsim, Avant! Verilint,
RealIntent Verex |
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Code Coverage - Synopsys Covermeter |
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test bench - in-house PLI-based and file-based
environments |
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Formal Equivalency Checking - Synopsys Formality |
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Formal Model Checking - Averant Solidify |
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RAMS - in-house, compiled (Artisan) , custom |
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Libraries - 3rd party (Artisan) |
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version control - Perforce |
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machine (queue) management - Platform LSF |
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Mixed Signal |
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Layout editor - Cadence Virtuoso |
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simulators – Nassda HSIM, Avant! Hspice,
Innologic ESP-CV |
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Substrate Design |
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Cadence APD |
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Layout |
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Avant! Apollo II P&R |
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Avant! Hercules II LVS/DRC |
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Avant! Star-RC 3D extractor |
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Synopsys Physical Compiler |
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Avant! Mars Rail |
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Power |
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Synopsys PowerCompiler |
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NVIDIA meets 3DFX who met GigaPixel |
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Similarities abound ! |
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The downsides (??) of near perfect retention |
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Try explaining everything you do ! … and why ! |
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The influence of your business model on your
design methodology |
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Damn, I wish I thought of that … |
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Always worried that we’re lucky and not good … |
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We have gotten good enough at the majority of
things that the problems that we have left once we hit silicon are really
tough !! |
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We are becoming increasingly biased toward
simple/predictable versus optimal |
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Absolutely still true – if you don’t test or
check it, it doesn’t work ! |
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Our biggest problem is “getting it right” |
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Convergence of methods to facilitate
verification |
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Formal and Simulation based methods will work
cooperatively |
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Logical and physical design will co-develop
versus today’s more serial process |
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Both physically-aware synthesis and
optimization-capable layout tools will coexist |
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All tools will need to embrace hierarchy to
avoid unmanageable dB size |
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Mass acceptance of higher-level language HDLs
will be preceeded by availability of high QOR behavioral compilers |
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LINUX based computing platforms will dominate
EDA |
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