[ What follows in NOT a paid advertisement. I've received no money,
no sexual favors, :^(, no nothing from anyone for this; it's purely
my own personal professional opinion. - John ]
Editor's Note: I would like to publically applaud Chronologic Simulation's
approach to doing business. Most EDA vendors put special clauses in their
licencing agreements to forbid customers from doing comparitive benchmarks
on their software. Also, most EDA vendors *say* that the vast majority of
their customers are repeat customers, they have very few bugs in their
products and those bugs they do have are fixed quickly -- you know, the
usual happy customer marketing drivel that's unconfirmable and perfect for
salesmen to use to convince you to buy their products.
In contrast, Chronologic Solutions actively encourages everyone to benchmark
their products. Now they're offering an upgrade from Verilog-XL to their
high speed Verilog simulator (VCS) for what works out to be $5000 ($1000 plus
$4000 maintanance) with a limit of one upgrade per engineering lab. Through
these *actions* Chrono is clearly showing that the vast majority of their
customers are repeat customers. They don't make money selling at this price;
their *actions* show they're confident they'll make money when you return to
buy a *second* VCS licence. They don't have a large aggressive sales staff
out to give you the hard sell; they let the benchmarks speak for themselves.
Also, because Chrono's a small company; you're not four beaureaucratic layers
away from the guy who wrote the code when you report a problem. Overall, I
see this as a company of engineers who wanted to make a screaming fast
Verilog simulator -- not businessmen out to make a
Synopsys VSS ## 1.0 quick buck in the EDA industry. Because
Mentor ## 1.1 Chronologic Solutions sells, in my opinion,
Viewlogic #### 2.0 a well supported kick-butt Verilog simulator,
Silicon Auto #### 2.1 I'm recommending you take advantage of
Cadence Turbo ####### 3.5 this upgrade offer before the January 31st
Vantage ######## 4.1 deadline. They're at 1-800-VERILOG.
Model Tech ######## 4.1
Cadence Leap ########### 5.4 - John Cooley
Simucad SILOS ########### 5.6 the ESNUG guy
Racal-Redac ################# 8.3
Chronologic ###################################################### 27.0 !
Relative Speed Benchmark of HDL Simulators (June 14, 1993 EE Times)
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