( ESNUG 192 Item 1 ) ---------------------------------------------- [8/12/94]
From: Ken.Kappeler@FtCollinsCO.NCR.COM (Ken Kappeler)
Subject: (ESNUG 191 #2) "Is Anyone Using The Synopsys Static Timing Analyzer?"
> And, is anyone really using Synopsys as a static timing analyzer?
> I don't find it accurate.
As an ASIC vendor, we have a small number of customers wanting to use
Synopsys as a static timing analyzer. In internal tests we have found
that with a correct SDF file, the timing analyzer is as good as the
numbers back-annotated. In prelayout, the timing will be subject to
the timing model chosen, the implementation of the ASIC library, and the
wire load model(s) provided. In postlayout, the only dependence is the
source of your SDF file and its correlation to silicon.
For NCR libraries and layouts we have seen good correlation between what
Synopsys static timing analysis reports and what is calculated and
reported by our timing calculator and layout tools. Admittedly we have
limited exposure to the Synopsys static timing analyzer to date.
I am interested in the limitations you found. Can you expand on this some
more on ESNUG?
- Ken Kappeler
NCR
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