( ESNUG 193 Item 4 ) ---------------------------------------------- [8/26/94]
From: don@westford.ccur.com (Don Monroe)
Subject: Interpreting Overlapping Verilog Casex Sectors
Does Design Compiler define how they implement overlapping selectors in a
Verilog "casex" statement? For example:
casex(var)
3'b1xx: action1;
3'bx1x: action2;
3'bxx1: action3;
3'b000: action4;
endcase
This is the syntax one would like to use for a one-hot state machine. Does
Synopsys ALWAYS generate the correct logic? If so, where is it documented?
- Don Monroe
Concurrent Computer Corp.
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