( ESNUG 195 Item 4 ) ---------------------------------------------- [9/23/94]
Subject: (ESNUG 193 #4) Interpreting Overlapping Verilog Casex Sectors
>Does Design Compiler define how they implement overlapping selectors in a
>Verilog "casex" statement? For example:
>
> casex(var)
> 3'b1xx: action1;
> 3'bx1x: action2;
> 3'bxx1: action3;
> 3'b000: action4;
> endcase
>
>This is the syntax one would like to use for a one-hot state machine. Does
>Synopsys ALWAYS generate the correct logic? If so, where is it documented?
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From: asic@netcom.netcom.com (Henry George Berkley)
In chapter 5 of HDL Compiler for Verilog Reference Manual:
"The first case-item that evaluates to 'true' determines the path.
All subsequent case-items are ignored, even if they are 'true'."
If you intend a one-hot state machine, use the '//synopsys parallel_case'
directive for optimal logic. ESNUG 193 Item 3 presents an excellent
example of a one-hot construction.
- Henry George Berkley
Electronic Consulting
P.S. Since the parallel_case directive logic behaves differently than
simulation, consider adding checking code:
//synopsys translate_off
begin : check_block
integer i, n;
n=0;
for ( i=0; i<3; i=i+1 )
if ( var[i] == 1'b1 )
n=n+1;
if ( n>1 )
$display("ERROR: var Bad one-hot state");
end
//synopsys translate_on
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From: martint@sei.com (Martin Taylor)
In the case syntax that the user orginally gave you would not get efficient
one-hot encoding. You would get an:
if then
else
else
else
Using the code example as supplied, the cases are evaluated in order until
one is found to be true. (To get one-hot encoding use the "// synopsys
parallel_case" directive. But be warned: If you use the parallel_case
directive then it is up to the engineer to guarantee *by*design* that only
one of the cases will evaluate true at any time.)
By the way; it's better to use casez than casex as x's in a casex are treated
as don't cares which can mask design errors.
- Martin Taylor
Silicon Engineering Inc.
---- ---- ---- ----
From: sgolson@trilobyte.com (Steve Golson)
In ESNUG 193 #4, the user wants to build a one-hot state machine, and wonders
if the following construct is guaranteed to work in Verilog:
casex(var)
3'b1xx: action1;
3'bx1x: action2;
3'bxx1: action3;
3'b000: action4;
endcase
A better idea is to use a "backwards" case statement:
case (1'b1) // synopsys parallel_case full_case
var[2]: action1 ;
var[1]: action2 ;
var[0]: action3 ;
default: action4 ;
endcase
This will do exactly what you want. (For more info see my paper "State
machine design techniques for Verilog and VHDL" in the most recent issue
of the Synopsys Journal of High-Level Design.)
- Steve Golson
Trilobyte Systems
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