( ESNUG 198 Item 4 ) ---------------------------------------------- [10/11/94]
From: [ Name Withheld ]
Subject: (ESNUG 195 #0 196 #2 197 #3) "Synopsys Announcing DesignPower"
(Egads, John! Post No name, No address, No nuthin' ... I suffer from
Synopcosis -- the fear of corporate reprisals from you know who.)
LSI Logic has had a power analysis tool for years, even prior to the mutation,
er, creation of VHDL. Originally called LPOW, (now called the Power Analyzer
in CMDE) it was designed to evaluate instantaneous dynamic power and average
it over time, it also reports power spikes.
The main problem with dynamic analysis is that the simulation stimulus must
mimic the actual circuit operation EXACTLY. Also, you must remember to
include proper output loading, as it will be in the system. Otherwise you
get trash for results. To increase your chances of getting things right,
remember to use asynchronous stimulus (i.e. not all of the signals of a data
bus arrive at the same time.)
Even with the best stimulus and models, don't expect better than 70-80%
accuracy from any such tool vs. the actual silicon.
- [ Name Witheld ]
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