( ESNUG 200 Item 1 ) ---------------------------------------------- [10/28/94]
Subject: (ESNUG 197 #3 198 #4 199 #5) "Static vs. Dynamic Power Analysis"
>>To increase your chances of getting things right, remember to use
>>asynchronous stimulus (i.e. not all of the signals of a data bus arrive
>>at the same time.)
>This may be exactly why an analytical (static) rather than an empirical
>(dynamic) power analyzer is needed: you *want* to hit the circuit with just
>the right timing so that the power spike is at its maximum. Any other
>scenarios are not as interesting.
From: [ No Name, No Nothin ]
Hi John,
You know me, no name, no address, no nuthin. I suffer from Synopcosis, fear
of corporate reprisals from you know who.
There is generally nothing interesting in a single power spike, except from
the EMI/EMC standpoint. I've had designs with 60W-100W power spikes in the
1-2 ns range and the result is 'so what'.
Remember the point of power analysis is to find the normal operation power,
not some theoretical maximum. In reality, a dynamic analyzer will show you
the biggest spike; it always occurs when you hit the first master reset in a
simulation. The analyzer will consider each unknown to known transistion to
be both a power consuming and power non-consuming event and then it will give
the min and max for that time. In my opinion, power analysis cannot be
accurately achieved via any static tool.
- [ No Name, No Nothin ]
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