( ESNUG 202 Item 5 ) ---------------------------------------------- [11/18/94]
From: jand@easics.be (Jan Decaluwe)
Subject: Synthesizable Yet Unsimulateble Verilog Code (!?)
VHDL/Verilog designers know the concept of non-synthesizable code: code
which is valid for the simulator but not for the synthesis tool. The
opposite should "by definition" not happen.
However, in a current project involving both Verilog and VHDL we
stumbled upon Verilog code which is synthesizable (Synopsys 3.0c) but
that cannot be simulated (Veriwell).
When trying to do "non-constant valued part-selects", like:
for (i=1; i <= 7; i=i+1) begin
a[i-1] = {b[7-i:0], zeros[i-1:0]};
end
the synthesis tool gives you the circuit you would expect, but the simulator
doesn't accept it!
I remember from my pre-VHDL life (3 years ago) that this is indeed a Verilog
restriction: part-selects should be "constant-valued". (It is still
documented as such in the HDL Compiler manual. A similar restriction is not
present in VHDL. Therefore, I guess this kind of code is synthesizable
because making it non-synthesizable would have been more work.) Anyway, my
conclusion is that this Verilog restriction is unnecessary & should be lifted.
Another possibility is that this restriction has already been lifted, but
that the enhancement has not found its way yet to the HDL Compiler
documentation and to my specific simulator. Anyone care to comment?
- Jan Decaluwe
Easics, BELGIUM
|
|
