( ESNUG 203 Item 3 ) ---------------------------------------------- [12/2/94]
From: mkphilli@netcom.com (Mike Phillips)
Subject: Model Tech & Synopsys VHDL Incompatibilities
John,
I have been back-annotating SDF delays generated by Synopsys into ModelTech's
VHDL simulator. The VHDL simulation library I was using was generated by
Synopsys Library Compiler (3.1a) and was created by the ASIC vendor I was
working with (ChipExpress). In doing this, I had to develop several scripts
in order to get Synopsys and ModelTech on the same wave length. One specific
problem was the names of the generic delay values. An example of a generic
in the VHDL simulation library is:
entity <macrocell> is
generic( <stuff deleted>
tsuD : Time := xx ns;
<stuff deleted> );
port( <stuff deleted> );
end <macrocell>;
Model Technology expects the generic to be "tsetup_d" instead of "tsuD".
(I wrote a script to substitute tsetup_d for tsuD in the simulation library
and everything worked o.k. In retrospect, I probably could have created
an alias, which would probably have worked and would probably would have been
easier to implement.) I'm not sure about is whether the ASIC vendor
was responsible for the generic being named tsuD instead of testup_d.
Maybe a Library Compiler expert out there knows the answer to this.
- Mike Phillips
E-Systems
|
|
