( ESNUG 204 Item 4 ) ---------------------------------------------- [12/9/94]
From: mr@symbionics.co.uk (Martin Ryder)
Subject: I Want To Get & Keep Real MUXes -- Not Logical Equivalents!
John,
I've got a situation where an asynchronous external signal must be sampled.
The signal comes from an A-to-D converter with variable sampling clock.
There is no fixed relationship between the ADC clock and the logic clock,
except that there are many cycles of the logic clock between each sample.
The ADC clock can shift across a range of +/- one CLK period, in steps of a
small fraction of a CLK period.
The requirement is easily met: use a MUX to hold the old sample until the
new sample has settled (the actual requirement includes peak-following...see
the VHDL fragment below). Using a MUX to block the ADC input during
transitions also means there's no meta-stability risk.
___________________ ________________________ ____________
TC_DATA_IN ___________________X________________________X____________
_ _ _ _ _ _ _ _ _ _ _ _ _ _
CLK _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
___ ___ ___
LOAD_PEAK _______| |__________________| |__________________| |_
(there are actually many more cycles of CLK between successive samples
than shown)
peak_reg : PROCESS (clk, tc_data_in)
VARIABLE abs_peak : signed(tc_data_in'RANGE);
BEGIN
abs_peak := abs( signed(tc_data_in) );
IF clk'EVENT AND (clk ='1') THEN
IF (peak_reset = '1') THEN
peak <= (OTHERS => '0');
ELSIF (load_peak = '1') THEN
IF (abs_peak > peak) THEN
peak <= abs_peak;
ELSE
peak <= peak;
END IF;
ELSE
peak <= peak;
END IF;
END IF;
END PROCESS peak_reg;
With v3.0c I get complex logic rather than MUXes: the synthesised circuit is
logically correct when all signals are static, but it does NOT block
TC_DATA_IN when (LOAD_PEAK = '0'). This puts transitions on the input of
the holding register whenever TC_DATA_IN changes (i.e. on every new sample.)
It's possible for this to happen close enough to the +ve edge of clk to
generate simulation violations, and also to create non-functioning silicon:
if bad data is sampled it screws up the rest of the system, it can't recover
even if it gets good data on the next cycle.
In v3.1b (same VHDL, same constraints, same library) I get MUXes, but the FAE
I contacted reckons this is down to slight differences in optimisation (i.e.
not a deliberate strategy to address this problem.) He has reproduced the
same structures I get, and has also created different structures from
slightly different releases of the same library! As a result I reckon my
safest option is to hand-place MUXes and then dont_touch them, but I'd like
a less clunky approach.....any suggestions?
- Martin Ryder
Symbionics Ltd
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