( ESNUG 205 Item 2 ) ---------------------------------------------- [12/16/94]
Subject: (ESNUG 204 #4) I Want Real MUXes -- Not Logical Equivalents!
>I've got a situation where an asynchronous external signal must be sampled.
>The signal comes from an A-to-D converter with variable sampling clock.
>There is no fixed relationship between the ADC clock and the logic clock,
>except that there are many cycles of the logic clock between each sample.
>The ADC clock can shift across a range of +/- one CLK period, in steps of a
>small fraction of a CLK period.
>The requirement is easily met: use a MUX to hold the old sample until the
>new sample has settled (the actual requirement includes peak-following...see
>the VHDL fragment below). Using a MUX to block the ADC input during
>transitions also means there's no meta-stability risk.
From: greg@cqt.com (Greg Bell)
How about just demetastablizing (sp?) the tc_data_in signal with F-F's
clocked with the logic clock? That's where you send the asynchronous signal
through a couple flip-flops in a row. This greatly reduces the chances that
the signal will be metastable by the time it gets into your design.
FF1 FF2
+---+ +---+
tc_data_in ----D Q-----D Q----> synchronized signal
+-C-+ +-C-+
logic_clk ------^---------^
Your solution *should* work though... Try synthesizing with no constraints
and see what you get. Maybe Synopsys is moving logic around in funny ways
trying to make your timing requirements.
- Greg Bell
CommQuest Technologies
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