( ESNUG 205 Item 6 ) ---------------------------------------------- [12/16/94]
From: ashok@parcom.ernet.in (B K Ashok)
Subject: Have To Hand Edit Timing Specs When Using FPGA Compiler
John,
How do I guide the FPGA compiler to write out the TNM path timing attribute?
XCAT 5.0 supports this new timing specification but I have no idea how do
I do that during synthesis process. I have tried to use path timing spec in
the Design Analyzer but if I do a compile after this, it appears that Synopsys
tries to build logic with that path constraint; It does not write out the TNM
time spec on the indivudal blocks. At present, I am manually editing the xtf
file and inserting the TNM attribute. Is there any way I can do that in the
dc_shell/design_analyzer?
- B.K.Ashok
Parcom
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