( ESNUG 206 Item 6 ) ---------------------------------------------- [1/13/95]

From: [ Anon ]
Subject: How To Get Design Compiler To Use D-latch w/ AND On Data Inputs

Hi John, (please keep me anonymous),

In our in-house good old standard cells library we have latchs with AND gates
on the data pin.  Is there some way to impose that Synopsys to use this AND
gate during HDL compilation?

                         ---    -------
                  A in---| & \__| D  Q |---- X out
                  B in---|   /  |      |
                         ---    | E    |
                                --------
                       enable ----'

  - [ Anon ]
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