( ESNUG 209 Item 1 ) ---------------------------------------------- [2/1/95]
Subject: (ESNUG 205 #5 206 #2 207 #4 208 #2) Synopsys->Mentor w/ "db2eddm" Sucks
>When we asked both Mentor & Synopsys about going from EDIF to EDDM, the
>answer was a definite "NO". We have encountered some problems with the
>db2eddm path (nets crossing bus rippers that were shorted in Mentor and not
>in Synopsys, etc.) Do you have any suggestions from any of your readers?
From: jco@egnetz.uebemc.siemens.de (Jon Connell)
John,
This used to be a major problem for us and meant that we had to upgrade to
the newest Design Compiler release as it became available. Since we started
using v3.2a to create our schematics, we've had no problems whatsoever! You
have to be careful if you're using an earlier Design Compiler release not to
create schematics since the earlier releases can break your sheets. Here's
the script I use to create my schematics:
echo_include_commands = "false"
single_group_per_sheet = "true"
bus_naming_style = "%s(%d)"
bus_range_separator_style = ":"
gen_cell_pin_name_separator = "_"
gen_match_ripper_wire_widths = "true"
suppress_errors = suppress_errors + { "NMA-16", "NMA-14" }
change_names -rules siff -hierarchy
create_schematic -hierarchy -rip_same_width -no_type_mappers -size infinite
The name rule "siff" is defined in $SYNOPSYS/admin/setup/.dc_name_rules as:
define_name_rules siff -special siff -collapse_name_space \
-replacement_char "_" \
-case_insensitive -max_length 29 \
-allowed "A-Z a-z _ 0-9 ()" \
-first_restricted "_ 0-9" -last_restricted "_"
Most of the problems in the earlier releases were Design Compiler defects and
they seem to be fixed now. Schematics are insanely complicated beasts so
there's still a chance that a design will break the schematic generator. If
it does, choosing a different sheet size or sorting the outputs will usually
fix the problem as this forces the generator to create the schematic
differently.
- Jon Connell
Siemens IC Design Center, Munich, Switzerland
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