( ESNUG 213 Item 4 ) ---------------------------------------------- [4/5/95]

From: frazer@idtinc.COM (Andrew Frazer)
Subject: Surprized By Model Tech/Synopsys VHDL Simulator Incompatibilities

Has anyone had experience with incompatabilities between VSS (Synopsys)
and VSIM (Model Technology)?

We developed a VHDL model in Model Tech's VSIM and completely debugged it.
When we ran the same model in Synopsys's VSS, we found that 20 out of 96 test
sets had some sort of miscompare.  I'm not surprised that different vendors
evaluate the VHDL language differently, but I'm surprised how difficult it is
find references detailing these differences.  Any help will be appreciated.

  - Andy Frazer
    Integrated Device Technology



 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)