( ESNUG 213 Item 5 ) ---------------------------------------------- [4/5/95]
From: kbpeh@tmi.com.sg (Boon Peh Keng)
Subject: Changed Timing Models & False Paths in >3.1 Latch Based Designs
Hi! John, I love your first few lines in each of the ESNUG posts!
Need a little bit of help here. I am not very experienced with Synopsys but
I have this problem which I never encountered with 3.1 and below. I think it
has something to do with their changing the Latch timing stuff.
Let say I have two one-bit registers, which can be read onto the data bus,
and written from it as well. The tool now seems to time from writing to one
of the registers, thru' its three-state driver onto the data bus, and back
onto the input of any one of the two registers, and it complained there was
not enough time at the end point. The path is of course a false one because I
do not expect the data to flow like that. How do I control this? Do I have
to define false paths for every one of such data latches? I am sure if
I had only one register, it will time from the point there was a write and
thru' the data bus and back to its own input. (This does not make sense
because I'd now have a feedback combinatorial circuit.) Setting the variable
level_sensitive_startpoint_close_active_edge = 1 seems to work. But is this
the right way? I am not doing "advance" latch-base design; I am just using
latches to hold data. (Incidentally, this two one-bit register exercise took
about 20 minutes to complete (but the library is huge) which is ridiculous.
----------------------
| |
| |----| |
----|D | |\ <------------ three-state driver controlled by rd1
| | QB|---| O-----|
---- | --|E | |/ |
wr1 | |----| | |
| L1 rd1 | 1-bit bus
| |
| |
| |
| |----| |
----|D | |\ |
| QB|---| O-----
---------|E | |/ <----------- three-state driver controlled by rd2
wr2 |----| |
L2 rd2
The path might be from active edge of wr1, plus max_borrow time, thru rd1
(three state driver) onto the bus and ends at D of L2. And complains about
data not valid in time for wr2. Note that wr1, and wr2 are both gated with
CLK. Any help/hint/pointers would be much appreciated.
- Boon Peh Keng
Tritech Microelectronic International, Singapore
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