( ESNUG 214 Item 2 ) ---------------------------------------------- [4/14/95]
Subject: (ESNUG 213 #5) "Timing Models/False Paths in 3.2 Latch Based Designs"
> ----------------------
> | |
> | |----| B1 |
> ----|D | in|\ out<--------- three-state driver controlled by rd1
> | | QB|---| O-----|
> ---- | --|E | |/ |
> wr1 | |----| | |
> | L1 rd1 | 1-bit bus
> | |
> | |----| B2 |
> ----|D | in|\ out |
> | QB|---| O-----
> ---------|E | |/ <----------- three-state driver controlled by rd2
> wr2 |----| |
> L2 rd2
>
>...Synopsys doing a timing analysis from wr1 -> thru the bus -> back into a
>latch--> back onto the bus. (DesignTime tries to time a false path from
>wr1 to QB of L1 to out of B1 onto the 1-bit bus and back to the D input
>of L1. This is a false path as this would result in feedback loop.)
From: pane@tubaman.STD.Teradyne.COM (John Pane)
I have a suggestion. Could you use:
remove_annotated_delay -from {L1/E,L1/D} -to B2/out
remove_annotated_delay -from {L2/E,L2/D} -to B1/out
I would think this would make synopsys focus on the prop-delay from
(L1/D or L1/E) -> B1/out and (L2/D or L2/E) -> B2/out.
- John Pane
Teradyne
---- ---- ---- ----
Peh Kheng Boon <kbpeh@tmi.com.sg> replies to the above suggestion with:
My concern is I have many many of these data latches. I have to then go and
figure out which would have this type of problem and set the constraint on
every one of them. Phew! That sucks. Secondly, it seems then I cannot
constraint the design from the HDL source. I must have a preliminary gate
implementation before I can try this method out -- otherwise Synopsys will go
crazy again. If I have special stuff like adders around, I would also have
the new problem that without constraints the adder Synopsys chooses may not
have the right architecture to meet my desired speed later!
Synopsys's on line help: "DesignTime Application Note: 2. Point-to-point and
Path Segmentation" suggested breaking the loop at the output of B1. Assuming
E is active low, one does:
set_output_delay <a number> -clock lclock -clock_fall find(pin, "B1/out")
This sets the timing requirement on the output of the driver rather than the
bus. (Wires wr1, wr2, rd1 and rd2 are all gated by "lclock" here.) This
breaks all existing paths through the three-state output pin. One should
then set realistic arrival time at the pin and appropriate cycle constraints
from the pin:
set_input_delay <a number> -clock lclock lbus set_multicycle_path \
-from find(pin, "B1/out")
One should be able to disable the feedback segment w/o affecting other paths:
set_false_path -from find(pin, "B1/out") -to all_registers(-data_pins)
Note I've assumed that the 1-bit bus is connected to a port called "lbus".
This method should work though I have not tried it out. However, this makes
things very messy because one needs to have a gate implementation before one
can do this.
- Peh Kheng Boon
TriTech Microelectronics International Pte Ltd, Singapore
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