( ESNUG 214 Item 5 ) ---------------------------------------------- [4/14/95]
From: dtkain@ccgate.hac.com (Dan Kain)
Subject: Specific Reasons Why Synopsys Sucks!
John, Synopsys synthesis sucks because:
1) It's Too Difficult To Use.
This is an entirely qualitative response which I feel needs some
rationale backup. In order to train a novice at our site to learn how
to run Synopsys synthesis, he/she will have to read the Synopsys VHDL
Compiler manual to learn how to write VHDL that Synopsys can read,
read the Design Compiler manual to write the timing & area constraints,
and read the Command Reference manual to really write the timing & area
constraints. After reading these manuals and perhaps taking a Synopsys
training class, the novice then has to find a Synopsys expert in our
organization that can really teach him/her how to run Synopsys. (I
compare this with our methodology of training a novice to run the Vantage
simulator. The novice sits down in front of a workstation with an
experienced Vantage user & learns how to run Vantage in about an hour.
Done.) -- I simply do not accept that synthesis is so difficult of a
process to run that it takes the learning investment that Synopsys
requires in order to accomplish the task.
2) It Consistently Dissapoints.
I have been running Synopsys synthesis tools since version 1.2. After
many years of fighting to get my VHDL code to successfully compile, and
after many years of iteration after iteration of changes to my timing
and area constraints to try to get a reasonable schematic in a reasonable
amount of CPU time, to date I have been continually dissapointed with my
final schematic outputs from the Synopsys synthesizer. (I again compare
this with my Vantage simulator experience. The code always compiles
except for my syntax errors. It always simulates correctly. Finally, it
has always done it in a reasonable amount of CPU time, even for some very
large designs.)
- Dan Kain
Hughes Aircraft Company
|
|
