( ESNUG 215 Item 1 ) ---------------------------------------------- [4/20/95]
Subject: (ESNUG 214 #6) Seeking Tools To Translate VHDL To Verilog
>
> Hi, John, -- do you know of any tool that translates VHDL to Verilog?
>
From: bolling@lds.loral.com (Randy Bolling)
John, I have seen Verilog->VHDL translators. The translation is pretty much
straight forward. But the syntax of VHDL contains complex data types not
found in Verilog. (Specifically, data typing and records manipulation would
be difficult. However, std_logic typed code that was synthesizable is
easily translated. For example, VHDL data type x contains n discrete values,
all modeled as log(base 4 of n) wires in Verilog. Issues like user resolved
data types with resolution functions would make for a hairy translation.
(Possibly requiring run-time support in Verilog in the form of a separate
Verilog "resolution" module.) All-in-all, not a good fit for completely
unconstrained VHDL.)
Why not buy Leapfrog with Verilog-XL model import, or Verilog-XL with
Leapfrog model import, or Precedence and connect Chronologic's VCS with say
Vantage or ModelTech, or seek out ModelTech/Mentor's newly announced
Verilog engine? While costly, it would solve the problem...
- Randy Bolling
Loral Data Systems
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From: eli@interhdl.com (Eli Sternheim)
Hi John,
InterHDL currently has a Verilog to VHDL translator. This translator covers
about 95% of the language, including the synthesizable subset. It has been
used by several companies to translate full designs from Verilog to VHDL
while preserving simulation results.
We're developing a translator from VHDL to Verilog. In the first stage, the
translator will cover the structural (gate level) subset. This one will be
available for beta test in early May. In the second stage, the translator
will cover the synthesizable subset of the language. This will be available
for beta in the third quarter of 1995. In the third stage, extensions will
be made to cover non-synthesizable features of the language, but the intent
is not to provide 100% coverage.
- Eli Sternheim
interHDL, Inc.
---- ---- ---- ----
From: jake@ascinc.com (Jake Karrfalt)
We at Alternative System Concepts in New Hampshire are developing a reverse
translator using the same parsing engine as our verilog2vhdl Translator.
The new product (to run on SUN and DOS platforms) is called vhdl2verilog and
will support a subset is going into beta soon. It's scheduled to ship in
late June 95. Price is in $6-8K range.
- Jake Karrfal
Alternative System Concepts
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From: jcooley@world.std.com (John Cooley)
Most Synopsys users already have on hand one of the world's most expensive
Verilog-to-VHDL and VHDL-to-Verilog translators available: it's called
"Design Compiler". Yup, just use for:
Verilog-to-VHDL: read -format verilog input_file.v
write -hierarchy -format vhdl -output output_file.vhd
VHDL-to-Verilog: analyze -format vhdl input_file.vhd
elaborate input_file
write -hierarchy -format verilog -output output_file.v
It's a little more complicated than this depending on exactly what/where
your VHDL libraries/packages are, etc. -- but you get the idea. (This is
just meant to show you a quick & dirty way to get simple translations.) You
won't get any fancy stuff through this conversion; just the synthesizable
subset with all timing information thrown away.
- John Cooley
the ESNUG guy
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