( ESNUG 215 Item 5 ) ---------------------------------------------- [4/20/95]
Subject: (ESNUG 214 #5) Specific Reasons Why Synopsys Sucks!
>John, Synopsys synthesis sucks because it's too difficult to use... a novice
>has to read the Synopsys VHDL Compiler manual to learn how to write VHDL
>that Synopsys can read, read the Design Compiler manual to write the timing
>& area constraints, and read the Command Reference manual to really write
>the timing & area constraints. ... the novice then has to find a Synopsys
>expert in our company who can really teach him/her how to run Synopsys. (I
>compare this with training a novice to run the Vantage simulator. The
>novice sits down in front of a workstation with an experienced Vantage user
>and learns how to run Vantage in about an hour. Done.) -- I simply do not
>accept that synthesis is so difficult of a process to run that it takes the
>learning investment that Synopsys requires in order to accomplish the task.
From: bolling@lds.loral.com (Randy Bolling)
John,
Compiling (or interpreting) and executing a language is straight forward
because its something with which most users are familiar. Few HW engineers
have avoided writing some language in their careers or in getting their
university degree. (We've all had to write *some* Assembly, C, FORTRAN,
COBOL, C++, or ADA.) This user must separate the process of simulation from
synthesis. How would a new user have any real-world metaphor or prior
experience upon which to use synthesis without first being shown the mapping
of language to gates?
New users must first learn the correlation between specific HDL constructs
and gates followed by learning how to use a synthesis tool to formulate that
mapping. After understanding the mapping, then comes the process of
optimizing the design. Every synthesis tool has these two stages. Thus, its
unfair to compare synthesis engines to simulation engines.
How to train individuals? Well, that could fill up a book of opinions...
- Randy Bolling
Loral Data Systems
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From: [ A non-Synopsys EDA Vendor ]
John,
Sorry to keep bothering you with mulitiple e-mails but in reading your most
recent ESNUG, I had to respond. As always, anonymous.
Someone should hit that user over the head with a two-by-four... I can
sympathize with the man but comparing ease of use of any synthesis tool with
a simulator is like comparing a Stealth to a Tonka Truck! Someday, the
process will be simple (and probably obsolete) and we'll look back, shake our
heads, and say "Work? You don't know what work is! I can remember when it
used to take three days to synthesize 500K ASICs from HDLs!" -- but that day
isn't now.
- [ A non-Synopsys EDA Vendor ]
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