( ESNUG 217 Item 3 ) ---------------------------------------------- [5/3/95]
Subject: (ESNUG 214 #6 215 #1) Seeking Tools To Translate VHDL To Verilog
>
> Hi, John, -- do you know of any tool that translates VHDL to Verilog?
>
From: peetj@hp7001.ecae.stortek.com (Peet James)
Vender Translation Tools:
About a year and half ago I tried a couple of the then available Verilog to
VHDL translators. All translated the model functionality fine, but timing
info (specify blocks) and comments were ignored. The translators also made
assumptions about mapping from various bit and bit vector specifications
into similar VHDL packaging specs. This made the resulting VHDL models
functionaly usable, but the timing and bit definitions were off. I found
the translation was a good place to start (I was translating a small
library at the time) and saved time -- but I had to heavily hand modify the
resulting VHDL to make it useable. These translators have been updated
several times since then, and some other players have also added new
translators. They might do more now.
Synopsys Library Compiler:
Later when I had to do the same thing on a larger library, I used the Library
Compiler to make functional equivelent VHDL models. Again, the embedded
timing info in the Verilog was lost, but in my case I did not need it (I was
using VHDL only on the RTL side of Synthesis, and Verilog on the gate side).
The resulting VHDL models had some compile problems with various simulators,
due to language interpretation differences, but that was easily fixed. The
bummer was that each time I got an updated version of the new library, I had
to recompile and re-fix all the little language differences. I scripted it
to make it easier, but each time it took a little manual intervention. If I
had to do this with adding timing info each time, it would have been to time
consuming to be usable.
Synopsys Design Compiler:
I have on various occasions, read in Verilog or VHDL RTL code, synthesized,
and then generated structural gates in the other. (In fact Reading in VHDL
and generating Verilog was our standard methodology.) Of course you need to
have purchased all the proper input and output compilers and generators
to do this. Fine if you have all of them like we do, costly if you do not.
Thought inquiring minds might want to know,
- Peet James
StorageTek
P.S.: Wished I could have been there to meet "Aart", "Harvey" & the sheep!
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