( ESNUG 218 Item 4 ) ---------------------------------------------- [5/19/95]
Subject: Design Compiler 3.2a Produces Bad/Incorrect Logic!
From: landman@hal.com (Howard Landman)
>
>Hi, John,
>
>We have found a serious bug in DC 3.2a which produces incorrect logic.
>The first symptom we had was that a certain input signal simply vanishes
>from the resulting circuit. (This made no sense since the signal is in
>fact used.) Later we were able to get "compile -verify" to admit that
>something was wrong:
>
> Information: Verification Failed. (OPT-103)
> Verification endpoint sv_reg[2]/next_state is different.
> A distinguishing pattern is:
> i11 : 1
> i12 : 1
> sv_reg[0]/Q : 1
> sv_reg[1]/Q : 1
> sv_reg[2]/Q : 0
> All other inputs may be assigned any value to distinguish the circuits.
>
>Following is the test case source code:
>
> input d,clk,a0,a1,a2,a3; output we_a; reg we_a;
>
> always @( posedge clk )
> if (d)
> case ({a0,a1}) // synopsys full_case
> 2'b0_1 : we_a = a2;
> 2'b1_0 : we_a = a3;
> endcase
> else we_a = 1'b0;
>
>I'm not including our library in the hope that this isn't library
>dependent ... my sense was that the bug happened quite early, perhaps
>even while reading in the Verilog (before compile). This bug does not
>seem to occur in 3.2b ... at least not for this case. I haven't tested
>it on any earlier releases.
>
> - Howard A. Landman
> HaL Computer Systems
From: [ The Synopsys Hotline ]
Hi John,
In v3.2a, you see feedback from the output of the "we_a" flip-flop. If
d = 0, the "we_a" flip-flop should be cleared. Instead, it keeps the
previous value of we_a (due to the feedback). When you input the design
in v3.1b of HDL Compiler, the logic looks fine.
This STAR (24439) is a duplicate of STAR 22402, a problem appearing in
another form. The problem occurs when a "case" statement with a
"full_case" directive is followed by another conditional statement (i.e.
an "if" statement, "else" branch or "case" statement) in the same process.
In the above example, an "else" branch follows a "case" statement that
uses the "full_case" directive, and as a result, you are seeing the bad
logic problem.
This problem is fixed in v3.2b.
There are three workarounds to this problem in v3.2a.
The first possible workaround is to input the Verilog code into v3.1b
of HDL Compiler and write out an unmapped .db in v3.1b. This unmapped
.db can then be input to v3.2a of Design Compiler, and further processing
can continue in v3.2a.
The second possible workaround is to remove the "full_case" directive,
and add a "default" statement to the "case" statement instead (or fully
specify the "case" statement). Following is the modified example:
input d,clk,a0,a1,a2,a3; output we_a; reg we_a;
always @( posedge clk )
if (d)
case ({a0,a1}) // full_case directive was here
2'b0_1 : we_a = a2;
2'b1_0 : we_a = a3;
default : we_a = 1'b0; // a "default" statement is added
endcase
else we_a = 1'b0;
If you have enumerated all the possible cases that can occur in the case
statement, you can modify the "default" statement shown in the above code
(module "works") to assign "x" (don't care) values to the outputs that get
assigned in the "case" statement. The modified code is as follows:
input d,clk,a0,a1,a2,a3; output we_a; reg we_a;
always @( posedge clk )
if (d)
case ({a0,a1}) // Note: full_case directive was here
2'b0_1 : we_a = a2;
2'b1_0 : we_a = a3;
default : we_a = 1'bx; // a "default" statement is added
endcase // Note: Output assigned to "x" instead of 0
else we_a = 1'b0;
This 2nd module is more efficient than the 1st module (above it) from a
synthesis perspective since no additional logic is generated for the
"default" condition. Please note, if a state is not covered in the
case statement, but occurs during simulation, x's will get introduced in
the system. Therefore, specifying "x" in the "default" statement is only
recommended when nonenumerated cases will not occur.
The third possible workaround is to modify the code so no conditional
statements appear following the "full_case" "case" statement in the same
"always" block. Following is the modified example:
input d,clk,a0,a1,a2,a3; output we_a; reg we_a;
always @( posedge clk )
begin
we_a = 1'b0;
if (d)
case ({a0,a1}) // synopsys full_case
2'b0_1 : we_a = a2;
2'b1_0 : we_a = a3;
endcase
end
My suggestion is to create a "default" statement for each case statement.
- [ Synopsys Hotline ]
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