( ESNUG 220 Item 3 ) ---------------------------------------------- [7/7/95]
Subject: (ESNUG 217 #5) How To Handle Timing Through Bidirectional Ports?
>How do other people handle timing through bidirection I/O's -- especially
>to/from an external RAM? I have a whole load of bogus loop paths through
>bidi's (I don't generate write data and clock it back in!). disable_timing
>only works to disable paths WITHIN cells, not between cells. set_false_path
>only works on path endpoints, so I can't just disable the piece of wire
>connecting the input pad's input to the output pad's output. SolvIt
>recommended doing set_input_delay and set_output_delay on the pins of the
>cells involved. This works, but it has a nasty side effect....
From: [ The Synopsys Support Center ]
John,
This is in regards to the issue of whether or not Synopsys tools can time
through pads to external RAMs. Several people within the company discussed
this, and we have two reasonable ideas on how to do this. No one has known
anyone who has attempted to time external RAMs using the Synopsys timing
analyzer. This does not mean no one has, but this may be the first to do it.
1) Use set_max_delay, with the -from and -to options specifying the
input_pad's input (or output) pin to the output pad's output(or input)
pin. The value of the delay constraint should be very large, to make
sure that the tool would not have any trouble seeing the path as meeting
constraints, no matter what. The advantage of this method is that it
is fast and easy. Set_max_delay is meant to constrain combinational
(not sequential) paths, so the -from and -to can specify most pins, not
just valid start points and end points. This also avoids any side
effects with clocks. The disadvantage is that the tool still thinks the
path is there, but as long as it meets constraints by a wide margin,
the tool will ignore it for timing and compilation.
2) Build your own Synopsys library component for the RAM, and time the chip
as a core block with the RAM next to it. This is what you suggested
originally. You don't need an LC license to build new cells with timing,
LC is only needed to describe functionality. This method would be much
more time-consuming, but its advantage is that any false path is
completely broken by the set_input_delay and set_output_delay commands
that are used as specified in the solvit article. The tool does not see
that path as existing. The effect on the tool is no different than
method 1, but some would call this the cleaner solution, because the
paths are gone, instead of being masked by a large set_max_delay.
In general, the set_max_delay would be easier for most bidir timing problems,
so we will put this into a solvit article, with a reference to the original
article that suggested breaking the timing paths.
- [ The Synopsys Support Center ]
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