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From: [ "an anonymous FPGA Compiler user" ]
Subject: Synthesizing FPGA w/ v3.3a Crashes While In v3.2 Everything's OK
John, for intra-company political reasons please have me be "an anonymous
FPGA Compiler user"; I don't want to get in trouble for this.
A number of engineers at my company have been getting crashes of Design
Compiler v3.3a with designs that ran just fine in v3.2. Usually the core
dump occurs in elaboration or in high level opto (before any FPGA tech
mapping). Have any other users reported instability in the production
v3.3a code compared to v3.2? Is the new version "fussier" about compiling
even if the code has warnings (not errors, but just warnings) during the
read or analyze/elaborate step? Any feedback would be great!
- [ "an anonymous FPGA Compiler user" ]
[ Editor's Note: I've also heard grumblings that v3.3a has been fatal city
for the non-FPGA (i.e. ASIC design) crowd using Design Compiler. - John ]
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