( ESNUG 223 Item 2 ) ---------------------------------------------- [7/26/95]
Subject: (ESNUG 222 #1) Verilog Parsers, full_case, parallel_case in 3.3a
>Personally, I hate the new Synopsys Verilog 3.3a parser. With the following:
>
> always@ (A0 or M)
> case (A0) // synopsys full_case
> 3'b 000 : z0 = 0;
> 3'b 001 : z0 = M[0];
> 3'b 010 : z0 = M[1];
> 3'b 100 : z0 = M[2];
> default : z0 = 1'bX;
> endcase
>
>It has a "default" statement therefore it is complete by definition -- yet I
>get the following message:
>
> Warning: You are using the \fBfull_case\fP directivewith a case
> statement in which not all cases are covered. (HDL-370)
>
>What is "\fBfull_case\fP" ?? Not all cases covered?? It has a "default"!
> (Fortunately, the resulting logic seems correct.)
From: celia@netcom.com (Celia Clause)
From my understanding of the synopsys full_case function, I would expect
some sort of warning from this code. From what I have read, and seen
generated, the full_case statement should normally ignore your default. You
have told the compiler that the case statement is fully defined (i.e. No
default condition is necessary.) If you take out the //synopsys full_case
you probably won't get the warning or you could get rid of the default, since
stating full_case implies a default of X for all unspecified cases anyway.
I am not actually using this version of Synopsys, so this is just a guess,
but the warning is probably just a clairification of the functionality that
already existed. (i.e. Use full_case or default, not both.)
- Celia Clause
---- ---- ---- ---- ---- ---- ----
From: [ No Muck Please ]
John,
Please don't use my name or direct e-mail. Just wanted to get another vote
in on the "parallel_case" and "full_case" compiler directives spitting out
that warning. (Synopsys & my company have a "cooperative" relationship, and
I'd rather stay out of the muck...) I tend to write state machines directly
as one-hot (with states defined as "000001", 000010", etc). I always
completely specify the case statements, and use full/parallel case to make
sure the logic is minimized. I, too, am now seeing these bogus warnings from
the 3.3a Verilog reader/parser.
I sent them a test case which they have received -- no resolution yet.
- [ No Muck Please ]
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