( ESNUG 223 Item 4 ) ---------------------------------------------- [7/26/95]
From: gregg.lahti@tempe.vlsi.com (Gregg Lahti)
Subject: DC's Lunar-Phase-&-Presidential-Approval-Rating Naming Schemes
John,
My serious gripes with Design Compiler is the inability to keep the naming
convention used in the VHDL code. This is especially painful if you would
like to keep the naming convention throughout the design so that you can
create seeding (placement) scripts in the backend of the layout process for
a tighter design, or just have more readable schematics/design for debugging.
For example, suppose we wish to plop down a 32-bit loadable register element.
This would be the easiest way to do this:
PCI_REG: process (clk) begin
if clk'event and clk='1' then
if load_pci='1' then
pci_reg(31 downto 0) <= pci(31 downto 0) after 1 ns;
end if;
end if;
end process PCI_REG;
Fine, except going through synthesis, Design Compiler decides to *randomly*
change the naming convention from PCI_REG to some UXXXX number. It also may
not keep the bit numbering convention, either if you decide to get fancy
with your generates or bussing scheme.
Hand instantiating the registers and then apply a "dont_touch" won't work,
either. Using the example below (muxed flop):
g1: for b in 0 to 31 generate
PCI_REG: mfntnb
port map ( da => pci(b), db => pci_reg(b), sa => load_pci, cp => clk,
q => pci_reg(b), qn => open);
end generate g1;
and applying "dont_touch { PCI_REG* }" command in dc_shell doesn't work.
Design Compiler again drops the naming convention and will implement
U-numbers in some random-use-the-lunar-phase-and-presidential-approval-rating
numbering scheme. It will also go and change the signal naming conventions
from pci_reg to U290_port_qn or something that relates to the changed
component name.
- Gregg Lahti
VLSI Technologies, Inc.
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