( ESNUG 223 Item 7 ) ---------------------------------------------- [7/26/95]
From: buco_fan@vnet.ibm.com (Anderson H. Hunt)
Subject: Parameterized Verilog Functions with Ranges, Defining & Calling
John,
I want to define a collection of n-bit Verilog functions where the value of
n is controled by a parameter. Something like:
function [n-1:0] flip_bus;
parameter n = 32;
input [n-1:0] a;
integer i;
for( i = 0; i < n ;i = i + 1 )
flip_bus[i] = DP_INVERT_D( a[i] ); // synopsys label f
endfunction
The problem is that 'n' in the 'function' statement doesn't get defined until
until the next line. The Synposys "HDL Compiler for Verilog Reference
Manual" seems to indicate the functions are allowed in functions, but doesn't
give any examples of how to override parameters in a function call. (The
reason I need to do functions instead of modules is that functions can be
instaniated conditionally unlike modules. This allows me to do growable
macros better (as in, fanout gets to big, throw in a buffer.))
- Andy Hunt
IBM
[ Editor's Note: This smells a lot like VHDL's "generic's"; if there's a
clever way to do this in Verilog, I'd be very interested. - John ]
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