( ESNUG 224 Item 1 ) ---------------------------------------------- [8/8/95]
Subject: (ESNUG 222 #4) BSDL File Creation
>Does anyone know of a 'good' way to generate a BSDL file to describe a design
>that's been built using Synopsys Test Compiler / Design Compiler ? Synopsys
>is talking about a product (feature) that does this automatically that will
>be introduced at some point in the future, but I'm looking for a more
>immediate solution that doesn't require us to create the BSDL files manually.
From: lombardi@ctron.com (Steven J. Lombardi)
John,
We are using a program (BSDLMaker) developed by Intellitech. We needed a tool
to create BSDL models of our ASICs for use on our JTAG tester (and also, as
Pete mentioned, did not want to create them manually). We brought in a company
called Intellitech (CJ Clark) to help us out. Intellitech developed a program
to take our gate level Verilog netlist and generate a BSDL file. I believe it
is now available for purchase (no, we don't have any affiliation with
Intellitech nor share in the sales profits of the software).
Our methodology used Synopsys Test Compiler to insert JTAG and we designed our
ASICs using LSI's 300K technology. In addition to generating the BSDL, it
performs some very helpful 1149.1 design compliance checks. The program is
easy to use and it works very well. They were open to suggestions during
development and supportive during beta and the initial release. You can reach
Intellitech at "cjclark@intellitech.com"
- Steve Lombardi
Cabletron Systems
[ Editor's Note: Intellitech is the company that gave out the Best Juvenile
DAC Freebie with its Super Soaker pistol, too! :^) - John ]
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