( ESNUG 226 Item 4 ) ---------------------------------------------- [8/31/95]
From: jms@vlsi9.gsfc.nasa.gov (Jeff Solomon)
Subject: Funky Toshiba/VSS VHDL Gate Simulation Methodology
Hey John,
This is Jeff Solomon, your favorite VHDL designer from the SNUG contest. :^)
I am currently taking a VHDL design through Synopsys 3.3b and to Toshiba's
0.7 micron tc170g gate array line. I have a question about their tool
pipeline from synthesis to gate level simulation. To perform gate level
simulation with Toshiba the following steps must be taken:
1. Synthesize gates
2. Write out VHDL netlist
3. Translate VHDL netlist to Toshiba's TDL netlist with Toshiba's vhdl2tdl
application program.
4. Run Toshiba's TDC (Toshiba Delay Calculator) to estimate all delays and
generate sdf file.
5. Use original VHDL netlist and sdf file just generated to simulate in VSS.
I have a few problems with this methodology:
1. Why can't I simply write out the VHDL netlist and the SDF file directly
from dc_shell and simulate that in VSS? It's a lot less steps.
If you say that I can't do that because TDC will give more accurate
delays than Synopsys's own timing analyzer then why did I bother
to set the constraints in Synopsys land if they are going to be
inacurrate? Stated a different way, if Synopsys timing analysis is
good enough for synthesis, why isn't it good enough for simulation?
Can you imagine the iterative process that a designer would have
to go through if the Synopsys timing analysis and the Toshiba
timing analysis were different? Even worse, since they probably
use two different algorithms, the results they return if they
are different will probably not be linear. That is, some delays
will be reported as faster and others as slower, try tweaking that!
(BTW, I have tried to use the Synopsys sdf file in VSS and it
just spews about primitives that couldn't be found. The least they
could do is make both sdf files work and tell you to try both)
2. TDC only allows the specification of a top level die size to estimate
the wire load. This means that TDC takes your whole netlist and
estimates all the wire lengths with no floorplanning information.
In Synopsys land, since you the designer have some idea what the
floor plan will look like, you can assign different size wire loads
to different sections to get a more accurate wire load estimation.
In TDC it seems that half the net will be underestimated and half
will be overestimated. Even if TDC makes guesses about floorplanning
bases on the explicit hierarchy, they might not be the right guesses.
John, I hope that I have explained my issues sucessfully. Do all vendors
have the same tool flow as Toshiba? Do you agree with my concerns?
- Jeff Solomon
NASA, Goddard
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