( ESNUG 227 Item 2 ) ---------------------------------------------- [10/13/95]
Subject: (ESNUG 225 #3 226 #2) Surprising Answer To A Metastability Question
>For the earlier question of a two-stage design versus a single-stage
>design at half the clock rate, THE SINGLE-STAGE DESIGN IS BETTER! The
>single stage design is better because it has an entire extra 25ns period
>(the difference between 40MHz and 20MHz) for the metastability event to
>resolve whereas the dual-stage design has only an extra 25ns - Tsu - Tpd.
>
>In terms of MTBF, the single stage design is better by a factor of:
>
> (Tsu+Tpd)/tau
> delta MTBF = e
>
>For example using Tsu=1ns Tpd=2ns tau=.2ns gives:
>
> delta MTBF = 3.3*10^6 times better!!!
From: vinu@atc.olivetti.com (Vinu Arumugham)
Hi John,
I think the performance of the two synchronizers in Bob's problem cannot be
usefully compared unless the frequencies of the core logic are the same. In
his problem, one design has a core frequency of 40 MHz, while the other is
shown running at 20 MHz.
For the same core logic frequency, the use of a single-stage synchronizer
clocked at half the frequency, would be twice as reliable as a design that
used a single-stage synchronizer clocked at the core frequency. That is,
we just changed the fclock parameter in the metastability equation by a
factor of 2, while the settling time available in both cases remained the
same. However, using a dual-stage synchronizer with both stages clocked at
the core frequency, will achieve an MTBF several orders of magnitude greater
than the single-stage cases.
CALCULATING DUAL-STAGE MTBF: The data input to the second-stage is
"asynchronous" only when the first stage is in a metastble state. The
average frequency of this occurence is (1 / MTBF) of the first stage.
Therefore, the MTBF of the second-stage can be calculated by replacing the
(2 * fdata) with (1 / MTBF) of the first stage in the standard single-stage
metastability equation.
CONCLUSION: If a designer has core logic running at frequency F and needs
to chose between single-stage synchronizers clocked at F/2 & dual-stage ones
clocked at F, the DUAL-STAGEs clocked at F would be the design of choice.
- Vinu Arumugham
Olivetti Advanced Technology Center
|
|
