( ESNUG 227 Item 4 ) ---------------------------------------------- [10/13/95]
From: ehlers@brooktree.com (Steve Ehlers)
Subject: Flakey 3.3a Compile Fatals & Sensitivity Lists
John,
I too have been experiencing fatal compile errors (ESNUG 220 #6 222 #1) in
the early optimization stage (Resource Allocation) with Synopsys 3.3a. In
the failing Verilog module I discovered that I had neglected to remove some
variables from a Verilog sensitivity list (as in, "always @ (var1 or var2
or var3)") after taking them out of the corresponding "case" statement. I
removed the un-used variables from the sensitivity list and the module
compiled fine.
Synopsys is really good for reporting variables that aren't in a sensitivity
list but should be. Maybe they could report unused or redundant variables
as well? While it shouldn't be their response to the fatal errors, it would
be good not to waste the simulation time consumed by evaluating a statement
needlessly.
- Steve Ehlers
Brooktree Corporation
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