( ESNUG 228 Item 3 ) ---------------------------------------------- [10/20/95]
Subject: (ESNUG 226 #4 227 #1) Funky Toshiba/VSS VHDL Gate Sim Methodology
> Synopsys modeling limitations. Each ASIC vendor has developed their own
> delay calculation algorithms over the past 10 years or so. Each method
> is considered by each company to be extremely proprietary. In order for
> Synopsys to be as accurate as all of these other delay calculators,
> Synopsys would have to put many different algorithms in the software.
> ... Putting all of these delay calculators into Synopsys will also give
> ASIC vendors immediate access to each others algorithms, which they would
> not like.
From: [Somewhere in Europe]
Not true. Synopsys only needs to allow ASIC vendors to link in their own
procedures to perform delay calculation, look at the methodology of the
DCL project, or Cadence's CDC. As 'No Name, No Nothing' correctly points
out, there is also the issue of wireload estimation and modelling, where
floorplan-based estimation would appear to be somewhat outside of the scope
of Synopsys' current capabilities.
However, at the moment, Synopsys appears to be the standard for delay
modelling amongst EDA vendors (how many vendors can translate timing
models from Synopsys?) and so Synopsys are unlikely to open up the format
when it appears to be giving them a competitive advantage. It does not
help the poor user, or the industry long-term!
Please keep me anonymous.
- [Somewhere in Europe]
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