( ESNUG 230 Item 4 ) ---------------------------------------------- [11/16/95]
Subject: ( ESNUG 229 #3 ) Dc_shell Does Verilog/VHDL Yet Fails To Output EDIF
> I've been trying to generate an EDIF netlist from the Synopsys' design
> compiler. But there seems to be something missing, as a result of which I'm
> getting a "write failed" when I try to generate edif netlist. Verilog or
> VHDL netlists come out fine for the same design. A sample session:
>
> dc_shell> write -format vhdl -output syn_out
> Information: Writing synthetic library implementations for design
> 'process1'. Use "write -no_implicit" to get just the design. (UID-172)
> 1
>
> dc_shell> write -format edif -output syn_out
> Information: Writing synthetic library implementations for design
> 'process1'. Use "write -no_implicit" to get just the design. (UID-172)
> Warning: Some designs have no schematic. (EDFO-1)
> Designs without schematics: process1_DW01_add_32_1 process1_DW01_add_32_0
> process1
>
> Nothing done.
> Error: Write command failed. (UID-25)
> 0
From: rray@msai.com (Russell Ray)
Hi, John.
Synopsys when writing out EDIF needs to have schematics generated unless
you set the edifout_netlist_only variable to true. Otherwise, it wants to
create an EDIF that is a schematic. So if you are not interested in having
EDIF schematics, set edifout_netlist_only to true and re-try writting out
the EDIF. Otherwise, you need to create_schematic -hierarchy before you do
the EDIF write.
- Russell Ray
Mitsubishi Semiconductor
---- ---- ---- ---- ---- ---- ----
From: rmehler@netcom.com (R. Mehler)
I think the problem here is lack of "netlist only" in the the script.
Just add "edifout_netlist_only = true" That might fix it.
- Ron Mehler
---- ---- ---- ---- ---- ---- ----
From: johne@vcd.hp.com (John Eaton)
Select your top level module and do: "create_schematic -hierarchy"
or you can manully click open each and every submodule in your design.
- John Eaton
Hewlet-Packard
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