( ESNUG 232 Item 2 ) ---------------------------------------------- [12/15/95]
Subject: (ESNUG 230 #6) "InterHDL's 'Verilint:' Good Stuff Or Trash?"
>We're evaluating "Verilint" which is supposed to flag pre-synthesis warnings
>in Verilog source code. We are told this tool is supposed to guide the user
>to writing better synthesizable code. We are really interested in hearing
>any feedback from people who have used this tool. We are not interested in
>the workings of the tool itself, but we would like to know if it actually
>helps you improve the quality of your code. For example, please don't just
>say "we've been using for N years and we like it". Please tell ESNUG what
>you like/dislike about it.
From: taub@corp.cirrus.com (Ed Taub)
John, I used verilint a few years ago.
Good: 1. Identified "relict" code i.e. variables no longer used, I/O not
connected, etc. 2. Detected subtle style errors like incomplete sensitivity
lists (nice but not critical.)
Bad: When I used it it emitted a storm of warnings, most useless. You could
limit the warnings from particular bugs but the mechanism was clumsy.
Ugly: The cost seemed excessive for the utility, in my case. (We were using
the Cadence synthesizer at the time and it had great synthesis style error
checking anyway. INHO Synopsys is not as great in error reporting either.)
- Ed Taub
Cirrus
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From: jhollins@eng.adaptec.com (Jack Hollins)
I insist that "Verilint" be run before simulation or synthesis on projects
that I am involved with. I don't believe it is productive to find syntax
errors by tying up an expensive verilog or synopsys license. Some of the
warnings it generates which I find most useful are:
1. sensitivity list omissions as this could result in mismatches between
rtl & synthesized simulations.
2. mismatches between size of arguments used in an assignment.
3. unused variables, macros , etc.
- Jack Hollins
Adaptec
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ANONYMOUS PLEASE!!!!!!!!!!!!!!
Likes: It finds things that Verilog (XL) doesn't catch and Synopsys may
or may not catch. e.g. a[0] <= #1 b[1:0]; Very quick to run.
Dislikes: InterHDL do not understand the unit-delay non-blocking design
methodology however the heinous warnings generated can be disabled.
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From: Chuck Gollnick <chuckg@arnet.com>
Verilint will find a lot of mistakes that could bite you later on, but those
reports are often burried amidst reams of trivial messages. You can
configure it to not generate certain messages, but that's kind of like
taking the battery out of the smoke detector because the little red light
keeps you awake.
Overall, I'd recommend using it because I think it will improve the quality
of your code and promote consistency between your various engineers.
- Chuck Gollnick
Digi International
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From: abdoo@azmda.sps.mot.com (Dave Abdoo)
John, We've had a Verilint license for a year or two now, and I always use
it on any code I've just written or changed. Why? Simple - it finds things
that Verilog won't flag as errors, but cause simulation issues. (And these
issues aren't always easy to find in sim!) Examples: floating nets,
assigning a vector'ed net to another signal of a different width, and (to
make this short) just about anything that can cause a failure that is due
to a brain fart, er, ah, oversight while creating your models. I personally
recommend it. When I changed jobs within my company, I nagged my new boss
into buying a copy for this group.
Note that a single floating Verilint license is plenty for most groups - it
runs so quickly that it's always available.
- Dave Abdoo
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From: dtozer@telenet.com (David Tozer)
John,
I have been using Verilint for a couple of years now; most recently Version
3.0 during the design of an FPGA. I see Verilint's main advantage as
identifying Verilog code which does not meet the syntax required by Synopsys.
This prevents the need to fix these problems as they are reported ONE AT A
TIME by the HDL Compiler. The source for the FPGA (28200 lines of code)
compiled, with no syntax errors, the first time I ran the HDL Compiler!
However, Verilint is extremely pedantic in its checking and reporting. This
is a good thing for the first couple of modules you write, but after that it
gets tiring to wade through pages of warnings (which you know are not
problems) to find the (hopefully) occasional error which is a problem. For
example, I put all my chip-wide `defines in one file which I include in all
my source modules. Verilint prints a warning for each `define which is not
used in the module.
I did use the Verilint command line options to disable some of the warnings
I was not interested in, but others had to stay because they might be
problems in certain circumstances.
To sum up; I use and like Verilint, its avoids having to debug Synopsys
syntax errors one at a time, but it does not make me write "better"
code - just syntactically correct code.
- Dave Tozer
Alcatel Data Networks
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From: irwans@videocore.com (Irwan L. Sie)
John,
I used Verilint a few times, around May 95, and my take on it:
- It is generally a good tool and will point out the same kinds
of code pblms that Synopsys would also find.
- If access to Synopsys license is limited, the value of Verilint
of course increases in aiding code development.
- Did I encounter any code pblms that Synopsys found and Verilint
didn't? No. All pblms were found by both.
- Did I encounter any code pblms that Verilint found and Synopsys
didn't? YES, BUT ACTUALLY NO. It was a Verilint BUG. Verilint
reported Timing Loops where there was none. I alerted the person
in contact with InterHDL then about this, they investigated, and
from what I gathered later on, they confirmed it, and I expect
that they have fixed it by now.
I did not use Verilint anymore after that brief evaluation.
- Irwan L. Sie
Videocore
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From: dblack@apple.com (David C. Black)
I use verilint and have the following comments:
* [POSITIVE] Its saved me many hours of needless compiles and simulations.
Verilint runs much faster than either the Verilog simulator or HDL compiler
for a much lower cost. Most runs take much less than a minute to complete
(see licensing comment below). Imagine a large simulation taking many
minutes to compile and finding a syntax error in the last file.
* [NEGATIVE] I have found that there are some errors missed by Verilint,
but caught by other tools. In other words, the set of errors caught by
Verilint, Verilog and HDL Compiler is an overlapping set, and Verilint is
NOT a superset.
* [POSITIVE] Verilint DOES catch errors missed by both Verilog and
Synopsys. Pays for itself.
* [POSITIVE] InterHDL's staff is extremely responsive to problems, and will
add tests once they are aware of them. You need to provide specific
examples, and there must be some automated method of detection. I have
seen suggestions implemented for the next release in very short order.
* [NEGATIVE] Verilint does not yet fully support Behavioral Compiler
(important if you use this). I am also certain that in general synthesis
checks apply primarily to Synopsys Design Compiler. Never-the-less they do
help.
* [POSITIVE] All warnings may be suppressed in a global or case by case
manner. Embedded comments may be used to suppress warnings that are "OK
for this design".
* [NEGATIVE] Some syntax errors have very little more than a pointer to
where. They could attempt to explain what the error was (missing semi).
Usually these are easy to spot.
* [POSITIVE] Errors and Warnings are succinctly stated on one per line.
* [POSITIVE] Invocation is identical to Cadence Verilog-XL. They use
identical switches (options) where possible.
* [NEGATIVE] Verilint-XL licensing has a poor licensing scheme. The first
time a user accesses Verilint-XL it locks that license to the user for 27
minutes to that user. During the 27 minute time period, the same user may
access verilint multiple times since they exclively own it. At the end of
27 minutes, another user can access it. This is fine if you have one
license per user. Unless you are buying one license per user, you should
definitely purchase Verilint-Turbo.
* [POSTIVE] Verilint-Turbo exists with the licensing restriction removed
(actually I think they reduced the time limit to a very small number). It
costs about twice Verilint-XL, but worth it.
- David C. Black
Apple Computer
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