( ESNUG 232 Item 5 ) ---------------------------------------------- [12/15/95]

From: dave@nlc.com (Dave Manley)
Subject: Why Doesn't Design Compiler Support `Ifdef, `Else, & `Endif ?

Can anyone give me one good reason why Synopsys chose to not support `ifdef,
`else, and `endif in the Verilog HDL compiler?  I'm using cpp but why should
I have to bother?

  - Dave Manley
    NLC
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