( ESNUG 234 Item 1 ) ---------------------------------------------- [3/14/96]
From: oren@waterloo.hp.com (Oren Rubinstein)
Subject: BUG w/ set_input_delay & set_output_delay w/ real & virtual clocks
Hello, John.
I just discovered a pretty fundamental bug in the way Design Compiler v3.3b
treats the delays that are relative to virtual clocks. Namely, a
"set_input_delay -min" relative to a real clock (port) will override a
"set_input_delay -max" relative to a virtual clock. (The same applies to
set_output_delay with "-min" & "-max" between real & virtual clocks.)
The result is that you get a design *with* violations, while Synopsys thinks
and tells you there are none!!!
Synopsys script:
create_clock CLK -period 15
set_drive 0 CLK
set_dont_touch_network CLK
create_clock -name fake_clk -period 15
set_input_delay 3 -max -clock CLK I1 /* #1 */
set_input_delay 14 -max -clock fake_clk -add_delay I1 /* #2 */
set_input_delay 1 -min -clock CLK I1 /* #3 overrides #2 !!! */
set_output_delay 13 -max -clock fake_clk O1 /* #4 */
set_output_delay -1 -min -clock CLK O1 /* #5 overrides #4 !!! */
Result of report_port:
Input Delay
Min Max Related Max
Input Port Rise Fall Rise Fall Clock Fanout
---------------------------------------------------------------
CLK -- -- -- -- -- --
I1 1.00 1.00 3.00 3.00 CLK --
^ ^
| |
these should be 14.00 not 3.00 !! -----------
Output Delay
Min Max Related Fanout
Output Port Rise Fall Rise Fall Clock Load
---------------------------------------------------------------
O1 -1.00 -1.00 -- -- CLK 0.00
^ ^
| |
these should be 13.00 not "--" !! -----------
The workaround is to group the constraints by clocks. In the example above,
swapping #2/#3 and #4/#5 in the script fixed the problem.
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
|
|
