( ESNUG 238 Item 8 ) ---------------------------------------------- [4/4/96]
From: benz@npss.enet.dec.com (Chuck Benz)
Subject: How Do You Synthesize To Glitchless Logic (Or At Least Test For It?)
Hi, John,
I'm wondering whether I can trust synthesis on generating logic that won't
glitch in one mode of operation, when there is another mode of operation in
which glitches are likely, and acceptable.
module glitch_or_no (clk, reset, data_a, data_b, select, mode, dataout) ;
input clk, reset, data_a, data_b, select, mode ;
output dataout ;
reg dataout ;
reg [3:0] count, count_D ;
always @ (posedge clk)
begin
if (!reset)
count <= 0 ;
else
count <= count_D ;
end
always @ (clk or reset or data_a or data_b or select or mode or count)
begin
dataout = data_a ;
if (mode && select)
dataout = data_b ;
if ((mode == 0) && (count == 4))
dataout = data_b ;
count_D = count + 1 ;
end
Clearly, the decoder of 'count == 4' can glitch when clk changes, if
'mode == 0'. But most of us can design logic that will not glitch dataout
if 'mode == 1'! (I know about the trivial design fix to pass dataout through
a flop, but I'm trying to avoid that because of the performance hit.) It's
just my luck the synthesis of this trivial example will probably result
in safe logic -- but, if I had something like this buried in a large design,
how do I know it will this *always* synthesize to glitch-free logic?
Are there tools, or ways to use Synopsys tools to ensure (or later determine)
that the result is safe ? More abstractly, can tools determine whether
glitchless operation is possible for a given RTL ?
- Chuck Benz
Digital Equipment Corp.
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