( ESNUG 239 Item 3 ) ---------------------------------------------- [4/11/96]
Subject: (ESNUG 238 #3) Three Ways To Port From Synopsys To Cadence Dracula
> How do other users run layout verification (such as Dracula) on a design that
> was synthesized with Synopsys? Synopsys writes out Verilog and VHDL
> netlists, but it does not write out the CDL (similar to Spice) format which
> Cadence's Dracula prefers. I know of three ways around this:
>
> 1.) tell Synopsys to create schematics, translate the output to a schematic
> tool (such as Viewlogic) through EDIF, then write out the CDL/Spice
> netlist from Viewlogic.
>
> 2.) use the Verilog netlist reader in Dracula's LOGLVS.
>
> 3.) write a home grown NAWK/C/Perl tool to translate the verilog netlist
> into CDL/Spice format.
From: jons@psdc.sps.mot.com (Jon Saari)
Hi John,
Here at our design center we use method number 1 as well ( however, we use
Cadence's Design Framework ). We have CDL views in our technology file, and
we dump a CDL/Spice netlist for verification.
- Jonathan K. Saari
Motorola
---- ---- ---- ---- ---- ----
From: Don Reid <donr@hpcvcdo.cv.hp.com>
John, We also had problems with the Verilog reader in LOGLVS. We use
our own netlist translator to write CDL/Spice.
- Don Reid
Hewlett Packard ICBD
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