( ESNUG 239 Item 6 ) ---------------------------------------------- [4/11/96]
Subject: (ESNUG 238 #8) How To Synthisize Or Test For Glitchless Logic
> I'm wondering whether I can trust synthesis on generating logic that won't
> glitch in one mode of operation, when there is another mode of operation in
> which glitches are likely, and acceptable.
From: kenr@yarmouth.engr.sgi.com (Ken Rose)
John, my understanding is that glitchless operation is not generally
guaranteed for combinatorial decoding. Whether an output glitches or not
depends on how the Karnaugh map is reduced; if the transition from one state
to another fits within the same reduced term, no glitch. Otherwise, without
a covering term connected one reduced state to another, there is potential
for a glitch. Here's an example:
\ BC 00 01 11 10
------------------
A 0| 1 | 1 | | |
------------------
1| | 1 | 1 | |
------------------
We can express this (using sum-of-products) as A'B' + AC. This may glitch
if there is a transition from ABC = 001 to 101. The glitch can be eliminated
by the covering term B'C, but SYNTHESIS WILL NEVER GENERATE THIS COVERING
TERM. (The reason is this 3rd term is redundant, and Synopsys avoids
redundant logic.)
As Chuck pointed out one way to avoid the glitch is to use a flop, but
contrary to his assertion about performance, it is possible to use the flop
without introducing a performance penalty. Suppose, for example, I want a
signal to be asserted when count is 4. By using a flop, and setting the flop
to 1 when the conditions for the count to *become* 4 on the next rising clock
edge are met. (I would write an equation that sets the registered signal to
1 when the count is 3 and all the other conditions for the count to advance
are met.)
The other advantage of this approach is the outputs are actually available
faster by predicting them. In the conventional design, the output delay is
the sum of clk->Q for the counter and the prop delay through the combo logic.
With the registered design, the delay is only clk->Q, which may help if the
signal goes off-chip to other logic.
- Ken Rose
Silicon Graphics Inc.
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From: amonti@vim.tlt.alcatel.it (Aurelio Monti)
Hi John,
My view is quite pragmatic: I try to avoid situations with glitchy logic.
You could design a gray counter instead of a binary one. You could also
change the encoding from binary to gray using state Design Compiler's FSM
state machine algorithms.
I, too, would like a tool to tell me whether a signal is generated from
unsafe combinatorial logic. (Sometimes it is not straightforward to check
this contraint by hand -- especially when your design is quite complex.)
I know this actually exists on something like gate level designs (see for
example LSI-Logic CMDE 'Design Critic' tool), but I'd like something not just
from one ASIC foundry and that can run those checks at the RTL level.
- Aurelio Monti
Alcatel Telettra
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