( ESNUG 240 Item 3 ) ---------------------------------------------- [5/9/96]
From: nickb@alpine.asic.sc.ti.com (Nicholas Barbieri)
Subject: What Does Power Compiler Really Get Us Power-wise?
John,
I'm mystified, so I need some assistance. I don't see why Synopsys is
putting so much effort into marketing Power Compiler. My experiments with
many designs (>20) show that core power typically accounts for less than
25% of the total chip power, with I/O and clock macro power the two
biggest consumers. If that is true, what difference will a few percent
saving from the core make? Is it worth buying an expensive tool? Are
there design examples that show a significant overall power savings? Not
being a battery-equipment designer, can anyone inform me by stating
definitively that such small savings make a difference in battery life?
When asked about this apparent disparity in demand for PC, Synopsys replied
that the other factors, such as external bus standards and RAM types, need
to be optimized to make power optimization of core logic more of a factor.
This seems after-the-fact to me, and frankly, unlikely to happen in most
cases. Do we have to redefine a PCI specification, for example, and spend
months optimizing custom RAM design to get any benefit out of PC? The
economics are unclear here.
On a related issue, I'm a bit disappointed in Synopsys' low-power design
methodology. It requires a significant amount of code modification by hand
to get low-power logic. Why can't they automate some of the techniques?
(As far as your comments about being edited, perhaps you should have added
a Java animation showing your tongue firmly planted in your cheek to your
message. I'm not a sexist, but I got the spirit of your humor.)
- Nick Barbieri
Texas Instruments
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