( ESNUG 240 Item 5 ) ---------------------------------------------- [5/9/96]
Subject: (ESNUG 238 #1 239 #2) The Change_names v3.3b Command Is A Real Dog!
> John, when we run the change_names command in Synopsys on our whole chip
> (somewhere in the neighborhood of 60K - 100K gates), it goes *very* slowly.
> ... When I say very slowly, I mean that it renames 1 net every 3 or 4
> seconds! The command takes roughly 24 hours to complete. ... The best
> workaround for this is...
From: David Ellement <ellement@sdd.hp.com>
Hello John,
ESNUG 239 arrived just at the right moment. We had just waited about thirty
hours for change_names to finish on our 110K gate design. I tried out the
suggestions, and the time to finish dropped to fifteen minutes! I tried both
'change_names_update_inst_tree = false' with writing out verilog,
'remove_design -all', then reading in the verilog net list rather than the
'db', and just the 'remove_design -all'. For our design, almost all the
improvement come from removing the design and starting again without
constraints. (I later re-apply the constraints to generate reports).
I couldn't be more pleased with ESNUG!
Finally, with respect to the comments by Mr. Christian, freedom of speech
is rather hollow without the freedom to offend. I'm glad there still
exists at least one forum where both you and Mr. Christian can express
yourselves, regardless of whether or not some may find it offensive.
- David Ellement
Hewlett Packard
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