( ESNUG 241 Item 3 ) ---------------------------------------------- [6/26/96]
Subject: ( ESNUG 240 #4 ) Backannotation Isn't Used By Floorplan Manager?
> My problem: I read in cluster files (PDEF) and 'set load' scripts & select
> a custom wire load model. When I do 'report_timing' from the *top level*
> of the hierarchical design I get indication about the clusters in the
> report & negative slack time. Yet when I do 'report_timing' *inside* a
> big module that I want to reoptimize (the whole design takes days) there
> is no indication that the report is using any backannotated data leaving
> my slack time positive!!?? (Likewise, 'reoptimize_design' on the sublevel
> finishes without doing much. I have the feeling that the backannotated
> data is not considered on any level other than the top level.)
From: rray@msai.mea.com (Russell Ray)
I'm not an expert on what is really happening but I ran into this same
problem with only using set_load and set_resistance commands. It appears
that the loads are only visible if the current design is set to the same
design as whey you performed the set_load commands. When the current design
is anything else, they are not taken into account.
The large amount of time spent re-optimizing is due to the fact that it is
off re-timing the design and using the wire_load models in the library being
used rather than seeing the back annotated information.
We had to use the characterize command from the top level to perform lower
level optimizations after back annotation. This seemed to be the only way
to get the back annotated data into our "compile -in_place_optimization".
- Russell Ray
Mitsubishi Semiconductor America, Inc.
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From: rnair@BayNetworks.COM (Rajesh Nair)
John,
Design Constraints, Timing constraints and any Backannotated parameters will
only apply in the context of the design to which it was applied. (Because
one could potentially be using the same subdesign in other designs or in
another context in the same design. In this case, you would not want the
backannotated value from the previous design to be present any more.)
In order to propagate constraints to a design down the hierarchy, you will
need to use the 'characterize' command on the particular instance from
your top level design.
- Rajesh Nair
Bay Networks, Inc.
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From: Andrew Inness <ainness@asic.sc.ti.com>
Hi John,
Yes, the custom wire load models created by Floorplan Manager are only used
by the same level that they were created at. This is similiar to the problem
that when constraints are annotated to a sub-block, they must be re-annotated
when you change levels of hierarchy. They will still be visible when using
the current_instance command to change levels of hierarchy for timing
reports, but they can not be used by the reoptimize_design at any other level
than where they were created.
There are two ways around this. One is to create the custom wire load models
from the top level, and then reassign them at the sub-level (with the
set_wire_load command) when needed. The main problem with this would
approach is that there may be a large number of models that would have to be
manually set all through the hierarchy. The second option would be to
use a script (either provided by your Si vendor, or written inhouse)
that will modify the set_load script to annotate the capacitance values
to whatever level of hierarchy that is needed, and then create the
custom wire loads at that level (for use with the reoptimize_design command
as well as the timing reports).
- Andy Inness
Texas Instruments, ASIC Applications
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