( ESNUG 241 Item 4 ) ---------------------------------------------- [6/26/96]
Subject: ( ESNUG 240 #3 ) What Does Power Compiler Really Get Us Power-wise?
> I'm mystified, so I need some assistance. I don't see why Synopsys is
> putting so much effort into marketing Power Compiler. My experiments with
> many designs (>20) show that core power typically accounts for less than
> 25% of the total chip power, with I/O and clock macro power the two
> biggest consumers. If that is true, what difference will a few percent
> saving from the core make? Is it worth buying an expensive tool? Are
> there design examples that show a significant overall power savings?
From: [ Synopsys' Sr. Low Power CAE ]
Hi John,
Specifically regarding power dissipation in clock networks; Power Compiler
does perform power optimization on the clock network. Power on a clock
network has two major components:
1. Power dissipation in clock buffer network (clock net + clock buffers)
2. Power dissipation within the driven elements (i.e sequential cells)
This power is the power dissipated internal to sequential elements
during clock transitions. Note that Power Compiler models the
situation when the clock transitions but the flip-flop output does not.
Power Compiler will work to reduce the power consumption in both the clock
buffer network (minus clock generator) and in the sequential elements.
Power Compiler will select (based on the switching activity, timing and DRC
constraints) the lowest power implementation for each sequential element
without violating timing or design rule constraints. Power Compiler will
also configure lower input pin capacitances (without violating timing or
design rule or clock skew constraints) for the cells connected to clock
network to reduce the power dissipation in clock network.
As pointed out by the user, I/O may be responsible for a significant
fraction of the total power dissipation, and design engineers may have
little flexibility to change I/O characteristics that are constrained by
system specifications. In these situations, core power reductions may
be the designer's only opportunity. In most applications where reduced
power consumption is a primary objective, system specifications will
reflect this goal by accomodating low-power I/O and memory technology,
as well as low-voltage power supplies. After the big power consumers
such as I/O and embedded memories have been addressed, core power
reductions represent a larger fraction of the the total power dissipation.
The solution which Synopsys currently offers starts with a gate level power
analysis tool (DesignPower). Using this tool, designers can analyze their
RTL architectures and perform "what if?" analysis. It is at the RT level
where significant reductions in power consumption can be achieved. It is
somewhat a manual process today.
Once a low power RTL has been selected, Power Compiler provides for an
additional push-button reduction in power. Power Compiler optimizes both
the sequential logic as well as the combinational power dissipation in the
synthesized portions of your design. These gate-level tradeoffs are done
automatically and doesn't introduce downstream issues such as testability
or clock tree synthesis problems.
Power Compiler is integrated with Synopsys' Links-to-Layout methodology.
All of synthesis is now power sensitive, including reoptimize_design with
Floorplan Manager. This means that after back-annotation of parasitics from
floor-planning, the critical path reoptimization and area recovery
algorithms are power sensitive (activity based). The ultimate result is the
lowest power implementation within your timing constraints.
- [ Synopsys' Sr. Low Power CAE ]
---- ---- ---- ---- ---- ---- ----
From: jcooley@world.std.com (John Cooley)
The basic reason why I was giving such excited comments about Power Compiler
was that it was the first tool to *pro-actively* enable designers to reduce
power consumption. That is, virtually all the currently available power
related EDA tools only do analysis and leave the designer with the classic
Oh-shit!-we-gotta-go-back-to-the-beginning-to-fix-this problem. Yea, sure,
a 10 - 15% power reduction may be chump change, but it's a beginning. I've
been on more than a few ASIC design projects where this would have saved us.
- John Cooley
the ESNUG guy
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