( ESNUG 243 Item 2 ) ---------------------------------------------- [7/17/96]
From: Oren Rubinstein <oren@waterloo.hp.com>
Subject: Synopsys 3.4b Won't Use 8->1 Multiplexers
John,
I wrote a test case for the infer_mux directive, with an 8-wide input:
module junk(clk, rst_n, e, i, o);
input clk, rst_n;
input [2:0] e;
input [7:0] i;
output o;
reg o;
// synopsys infer_mux "mux1"
always @(posedge clk) begin: mux1
if(!rst_n)
o <= #1 1'b1;
else case(e)
3'b000: o <= #1 i[0];
3'b001: o <= #1 i[1];
3'b010: o <= #1 i[2];
3'b011: o <= #1 i[3];
3'b100: o <= #1 i[4];
3'b101: o <= #1 i[5];
3'b110: o <= #1 i[6];
3'b111: o <= #1 i[7];
endcase
end
endmodule
It works (i.e. it builds MUX trees) but it will not use an 8->1 MUX!
Instead, it builds a 2 stage tree, with the input stage containing 4
2->1 MUXes and the output stage containing a 4->1 MUX. The design is
underconstrained from the timing point of view, and has a set_max_area 0.
From the area point of view, the order of efficiency is:
8->1 MUX ............ smallest area
4 2->1 + one 4->1 ... 21% bigger than 8->1 .... yet this one chosen
2 4->1 + one 2->1 ... 23% bigger than 8->1
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
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