( ESNUG 243 Item 6 ) ---------------------------------------------- [7/17/96]
Subject: ( ESNUG 241 #7) We Like Avant! But Don't Know About The Lawyers
> We've looked at a couple of products and even asked some vendors to try out
> one of our 60K gate designs. Compass still haven't come back with
> Pathfinder results. Cadence Cell3 results are fairly impressive (12%
> smaller than our Cell Ensemble and the job took about 1/30th of the
> original P&R time!) Avant! ArcCellBV and ArcCellXO were both even better
> than Cell3. ... Our problem is how can we do business with the
> Avant!/Cadence lawsuit looming? Is there any way an Avant! customer can
> get burned if they lose?
From: "Guntram Wolski" <gwolsk@sei.com>
Hi John,
I, too, was interested/impressed with Avant! at DAC -- even said so in my
trip report at SEI. This lawsuit is just unfortunate as it does make
everyone I talked to wonder about the tools. Worst case though, might it
not go the way of the Intel/AMD ucode lawsuit where AMD was required to just
rewrite the sections of ucode that were considered offensive? Yea, like I'm
a lawyer... :-)
- Guntram Wolski
Silicon Engineering, Inc.
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From: jcooley@world.std.com (John Cooley)
This issue got me so curious that I called up some of the long time industry
watchers (EDA users, lawyers, editors, executives, investment bankers, etc.)
and came up with the following 3 possible outcomes:
1.) Cadence Loses Hands Down: Joe Costello resigns and joins the French
Foreign Legion under the assumed name of "D'Artagnan Dumas" never to
be heard from again. Avant! customers go on with business as usual.
2.) Cadence Gets Its Injunction, Etc: Gerry Hsu skips town 10 minutes
before the police come to get him and is last rumored to be living as a
Buddist monk in Tibet. Avant! can no longer sell the products named
in the court order thus leaving its customers in the lurch. Since
I can't find anyone who can think of even one case where customers of
a high tech copyright infringed product were held liable, it seems
unlikely, in my non-legal opinion, that Avant! customers would lose
more than the use of the product. I just can't see Cadence successfully
bringing those Avant! customers with huge legal staffs (like Motorola,
Seimens, Alcatel, AMD, and Toshiba) to court and surviving unscathed.
3.) Most Likely: both sides work the American legal system for what it's
really good at -- dragging lawsuits out ad nauseum. Eventually both
sides get bored and mutually decide either to settle out of court for
a lump of money or to just stop wasting so much money on lawyers.
No, I'm not a lawyer, nor do I work at Dionne Warwicke's Psychic Friends
Network; so my advice is not legal and I can't predict the future. But, if
I believed that the Avant! tool was far better (I can't say; I haven't used
it) I'd buy it after haggling the price way down for fear of suddenly losing
it. That is, I've got to constantly use the most productive EDA tools
because if I don't and my competitors do, I'm in worst trouble.
- John Cooley
the ESNUG guy
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From: [ The Thin Man ]
Hi John -- Please keep me anonymous.
Let me start by saying that choice of layout tool appears to be a religion
war -- make the wrong selection and you are a heretic! As a designer (rather
than a layout priest) I would have to say that the easiest toolset to use is
either the Compass tool-set or the Cascade tool set, as neither of these
tools require the mysterious incantations required by the Cadence or
Avant! tools. This means that they are accessible to us mere mortals who are
more interested in completing a design rather than spending many hours in
layout ping-pong.
We have over the past few years used/compared the Cadence/Avant!/Compass
and Cascade tools for several benchmarks and real designs and found the
Cascade tools to be the easiest to use, well integrated with a Synopsys based
design flow, and give results comparable to any of the other layout systems.
(In our benchmarks they beat Avant! and Compass on some designs.)
Cascade takes as input a hierarchical Verilog or VHDL netlist (and maintains
the hierarchy throughout the layout operation - including clock tree
generation). It has a built in floorplanner which accepts layout directives
in the same way that Synopsys accepts compile directives in the netlist (or
attributes can be added during the manual floorplanning effort). The initial
floorplan is automatically created and although not always optimal it forms
a good starting point for the final floorplan - in the case of small blocks
(> 10K gates) it usually produces an optimal layout.
There is a Synopsys supported interface to generate custom wire load models,
set_load commands and more importantly the interface takes the output from a
"write_script" command and translates them into timing directives for the
layout timing objectives (i.e set clocks, input delays, output delays, etc.)
Synopsys libraries in either cmos2 or lut are provided as part of the
technology rule-set.
The best feature from a designers point of view is probably the integrated
delay calculation and timing analysis tools, these are linked to the layout
tools so that after a layout is completed the design can be examined for the
usual timing problems.
Timing issues can be addressed by increasing or decreasing the drive
strengths of gates along critical (or specified) paths, this feature (known
as timing driven buffer sizing) means you do not have to return to Synopsys
to fix setup/hold violations or speed up critical paths - buffer sizes are
changed in the layout via commands in the timing analysis tool.
I would reccomend you take a look at the Cascade tools to see if they fit
your requirements - and no I don't work for them I just think they have a
great tool set - there is also more likelihood of being able to complete
your layout without the assistance of a lawyer !
- [ The Thin Man ]
[ Editor's Note: This "Thin Man" letter came from a user's address - John ]
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