( ESNUG 243 Item 7 ) ---------------------------------------------- [7/17/96]
Subject: ( ESNUG 241 #10) "Gotchas" Using Mixed Mode Cadence With LMC Models
> I am currentlydoing a mixed-signal simulation using Cadence Concept, Logic
> Work Bench (used in Mixed Signal mode), Leapfrog, and Verilog-XL (all of
> which are from release 9502.)
>
> The Synopsys LMC models I'm using include the old-fashioned Verilog
> Smartmodels (Release 39) and the generic SWIFTModels (Release 40). We are
> in the process of obtaining & installing SWIFTModel Release 40b (this has
> Concept symbols for the devices being modeled) and VHDL SWIFTModel Release
> 8. (I do not intend to use the Verilog models because they will not be
> supported after this year.) ... What are the gotchas in this approach?
From: Randy Bolling <randy@vela.com>
John,
I am not certain of the "mixed simulation" application, as most of the
simulation effort is focused around a digital application. By mixed mode,
I assume mixed VHDL/Verilog/hand-generated gates.
The process is among the best for "generic sign-off", offering up performance
gains for using Verilog-XL's presence at sign-off. Naturally, intensive
regression analysis will notice significant improvements with other Verilog
simulators (even ones offered from Cadence), which may lack the sign-off
status but suffice for voluminous simulation.
Cadence has not been known for their visibility down through Verilog-XL into
Leapfrog VHDL, or visa-versa, down through Leapfrog VHDL into Verilog-XL.
They have previously lacked features allowing debug of the "imported"
code due to the fact that Concept was applying a PLMI interface,
not a complete debug environment. Tracing signals around the Verilog
netlist after synthesis (assuming you sign-off Verilog, and synthesize
VHDL) can be difficult; tasks such as injecting values onto signals and
tracing signals in simulation time. Viewing vectors is no more different
than usual with Verilog-XL.
Finally, debugging a netlist without at least a viewable netlist can be
difficult. Last I checked, there were no direct paths from Synopsys to
Concept schematic diagrams (Composer yes, Concept no.) Thus, you can always
view the netlist in Synopsys Design_Analyzer (as many do) until you become
familiar with the netlist format. A dedicated Design_Analyzer license
becomes valuable at this point.
If you feel comfortable, an alternative approach is ModelTech for the
heterogeneous mix of VHDL/Verilog code during debug, and sign-off on a single
copy of Leapfrog/Verilog-XL/Concept/LMC/Logic Workbench. ModelTech offers a
consistent interface for both Verilog and VHDL simulation and debug.
Optionally, you can create a singular Verilog world thus making the problem
much simpler by eliminating the need for imported or mixed simulation.
This would allow for the use of a number of alternative Verilog simulators.
Hope this helps out in some manner.
- Randy Bolling
Vela Research
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