( ESNUG 244 Item 2 ) ---------------------------------------------- [7/25/96]
Subject: ( ESNUG 243 #8 ) VHDL Compiler Problems w/ Generics & Aggregates
>It gives the error:
>
> Error: Cannot determine type of the aggregate
> in routine top line 55 in file '...../ex.vhd'
> (This error can occur if an aggregate and a generic appear in the
> same component instantiation.) (HDL-206)
>
>When will Design/VHDL Compiler better support generics & aggregates?
From: Christopher Papademetrious <st92j0gw@dunx1.ocs.drexel.edu>
John,
We encountered the exact same thing. A slightly inelegant solution we used
was to assign a signal the correct aggregate of signals, then assign this
new signal as a whole to the port in the generic design. This was slightly
annoying, since our data-driven design had MANY ports of varying length,
with many sub-fields coming from different places, and required this kludge
everywhere to come together cleanly.
- Chris Papademetrious
Drexel University
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From: "Serge.Martin" <serge.martin@cns.cnet.fr>
Hi John,
At CNET we too found it very frustrating to be limited by such "features".
What's worse is that most of the subset restrictions concerning structural
VHDL are not due to the synthesis process itself, but rather due to
limitations of ellaboration phase of Design_Compiler.
Rather than waiting for Synopsys to extend their synthesizable subsets, we
started using LEDA's HELIOS tool that allows such structural constructs to
be used for synthesis. HELIOS accepts VHDL (87 and 93) models expanding
features such as the use of generic parameters, the types of generic
parameters used, the bounds of generate statements, the use of full
configurations, and the use of complex expressions (including file I/O) to
initialize constants. (HELIOS generates an equivalent VHDL model that has
all of these features removed and is accepted by VHDL Compiler.)
- Serge MARTIN
FRANCE Telecom CNET Grenoble
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[ Editor's Note: What follows is a related exchange of e-mails. - John ]
From: wyamamo@ibm.net (Wataru Yamamoto) to Kevin OBrien of LEDA:
> Mr. O'Brien, Does HELIOS convert the following description to Synopsys-
> VHDL-compiler-acceptable one?
>
> entity ex is
> port(p00: out std_logic_vector(0 to 8));
> end ex;
> architecture another_question of ex is
> begin
> p00(3 to 7) <= (others=>'0'); -- VHDL compiler hates this!(maybe)
> end another_question;
From: Kevin OBrien <kevin@leda.fr> to Yamamoto-san:
> Yamamoto-san, I ran your example through HELIOS. The results are:
>
> entity EX is
> port(signal P00 : out STD_LOGIC_VECTOR ( NATURAL range 0 to 8 ));
> end EX ;
> architecture ANOTHER_QUESTION of EX is
> begin
> P00 (NATURAL range 3 to 7 ) <= (3 to 7 => '0' );
> end ANOTHER_QUESTION ;
From: wyamamo@ibm.net (Wataru Yamamoto) to Kevin OBrien of LEDA:
> The above is not acceptable to Synopsys. :^( I expected the following,
> which is acceptable:
>
> architecture ANOTHER_QUESTION of EX is
> begin
> P00 (3) <= '0';
> P00 (4) <= '0';
> P00 (5) <= '0';
> P00 (6) <= '0';
> P00 (7) <= '0';
> end ANOTHER_QUESTION ;
From: Kevin OBrien <kevin@leda.fr> to Yamamoto-san:
You're beginning to touch on a very sensitive subject in VHDL circles: what
constitutes the synthesizable VHDL subset. The IEEE is currently in the
process of defining the syntax and semantics of such a subset and until such
time as they do, we will always have problems like the one you mention.
Each synthesis tool has many different idiosynchrasies. HELIOS was designed
as an "elaboration tool for synthesis", not as an "elaboration tool for
synthesis with Synopsys". 99% of the time this is the same thing, but as you
pointed out, there are always exceptions.
The difference between the result generated by HELIOS and that accepted by
VHDL Compiler for your example is very small and such differences could be
removed quite easily. It is not too difficult to envisage a -s option added
to HELIOS for Synopsys-specific elaboration to perform such transformations.
This would necessitate a small amount of development by us. As all such
development is based on user demands, if there is a big enough demand for
such an option, we'll develop it!
- Kevin O'Brien
LEDA
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