( ESNUG 246 Item 2 ) ---------------------------------------------- [8/8/96]
Subject: (ESNUG 243 #2) Synopsys 3.4b Won't Use 8->1 Multiplexers
>I wrote a test case for the infer_mux directive ... It works (i.e. it builds
>MUX trees) but it will not use an 8->1 MUX! Instead, it builds a 2 stage
>tree, with the input stage containing 4 2->1 MUXes and the output stage
>containing a 4->1 MUX. The design is underconstrained from the timing point
>of view, and has a set_max_area 0. From the area point of view, the order
>of efficiency is:
>
> 8->1 MUX ............ smallest area
> 4 2->1 + one 4->1 ... 21% bigger than 8->1 .... yet this one chosen
> 2 4->1 + one 2->1 ... 23% bigger than 8->1
From: Martin Soques <Martin.Soques@amd.com>
John,
The mux tree solution may not be necessarily bad from a routing point of
view. From my experience, I've found that large N->1 mux cells can result
in routing congestion in the vicinity of the mux cell due to the large
number of signals required by the mux. I'll take the silicon hit to avoid
routing problems due to the mux congestion.
- Marty Soques
Advanced Micro Devices
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From: rudis@intrinsix.com (Romas Rudis)
Hey John,
Synopsys can not automatically map anything with more than 8 inputs into a
logic funtion. Therefore an 8:1 mux (which has 8+3=11 inputs) will never
get chosen! You must actually instantiate it like so:
// Using Synopsys designware to make a 4 bit wide 8:1 MUX
GTECH_MUX8 mux0(.A(I_sel[0]),.B(I_sel[1]),.C(I_sel[2]),
.D0(I_a[0]),.D1(I_b[0]),.D2(I_c[0]),.D3(I_d[0]),
.D4(I_e[0]),.D5(I_f[0]),.D6(I_g[0]),.D7(I_h[0]),.Z(O_y[0]));
GTECH_MUX8 mux1(.A(I_sel[0]),.B(I_sel[1]),.C(I_sel[2]),
.D0(I_a[1]),.D1(I_b[1]),.D2(I_c[1]),.D3(I_d[1]),
.D4(I_e[1]),.D5(I_f[1]),.D6(I_g[1]),.D7(I_h[1]),.Z(O_y[1]));
GTECH_MUX8 mux2(.A(I_sel[0]),.B(I_sel[1]),.C(I_sel[2]),
.D0(I_a[2]),.D1(I_b[2]),.D2(I_c[2]),.D3(I_d[2]),
.D4(I_e[2]),.D5(I_f[2]),.D6(I_g[2]),.D7(I_h[2]),.Z(O_y[2]));
GTECH_MUX8 mux3(.A(I_sel[0]),.B(I_sel[1]),.C(I_sel[2]),
.D0(I_a[3]),.D1(I_b[3]),.D2(I_c[3]),.D3(I_d[3]),
.D4(I_e[3]),.D5(I_f[3]),.D6(I_g[3]),.D7(I_h[3]),.Z(O_y[3]));
/* sample constraint file for above example */
set_prefer {lca500kv/MUX81 lca500kv/MUX81P}
set_map_only find(reference, GTECH_MUX8)
set_max_delay 2.00 -from I_sel -to O_y
set_max_delay 1.00 -from {I_a I_b I_c I_d I_e I_f I_g I_h} -to O_y
Unfortunately there is no easy way to instantiate multiple components in
Verilog (in VHDL you can use "generate" statements, but even this is crude.)
I have built a user designware module called "mux_gen" where you can just
pass parameters and get one built like you want. (Note: Kurt Baty has
created a module he calls "mux_any", while mine is similar in function, it
uses a different algorithm). I am in the final phases of testing it and
getting it a releaseable form.
An example of how to use mux_gen appears below:
// Instantiate a 16-bit wide 8:1 mux, #(select_lines,bit_width)
mux_gen #(3,16)
mux_u1({I_h,I_g,I_f,I_e,I_d,I_c,I_b,I_a},I_sel,O_y);
If you would like a copy please e-mail me.
- Romas Rudis
Intrinsix Corp.
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